changes access to rounding mode to fail explicitly instead of unintended behavior

mostly about ensuring correct sign

.clang-format

@@ -1,4 +1,3 @@
----
 Language:        Cpp
 # BasedOnStyle:  LLVM
 # should be in line with IndentWidth
@@ -13,8 +12,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
 AllowShortBlocksOnASingleLine: false
 AllowShortCaseLabelsOnASingleLine: false
 AllowShortFunctionsOnASingleLine: All
-AllowShortIfStatementsOnASingleLine: true
-AllowShortLoopsOnASingleLine: true
+AllowShortIfStatementsOnASingleLine: false
+AllowShortLoopsOnASingleLine: false
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
 AlwaysBreakBeforeMultilineStrings: false
@@ -39,8 +38,8 @@ BreakBeforeTernaryOperators: true
 BreakConstructorInitializersBeforeComma: true
 BreakAfterJavaFieldAnnotations: false
 BreakStringLiterals: true
-ColumnLimit:     120
-CommentPragmas:  '^ IWYU pragma:'
+ColumnLimit:     140
+CommentPragmas:  '^( IWYU pragma:| @suppress)'
 ConstructorInitializerAllOnOneLineOrOnePerLine: false
 ConstructorInitializerIndentWidth: 0
 ContinuationIndentWidth: 4
@@ -76,13 +75,13 @@ PenaltyBreakFirstLessLess: 120
 PenaltyBreakString: 1000
 PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
-PointerAlignment: Right
+PointerAlignment: Left
 ReflowComments:  true
 SortIncludes:    true
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
 SpaceBeforeAssignmentOperators: true
-SpaceBeforeParens: ControlStatements
+SpaceBeforeParens: Never
 SpaceInEmptyParentheses: false
 SpacesBeforeTrailingComments: 1
 SpacesInAngles:  false

.gitignore

@@ -1,5 +1,6 @@
 .DS_Store
 /*.il
+/.settings
 /avr-instr.html
 /blink.S
 /flash.*
@@ -14,7 +15,6 @@
 /*.ods
 /build*/
 /*.logs
-language.settings.xml
 /*.gtkw
 /Debug wo LLVM/
 /*.txdb
@@ -30,4 +30,5 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
-/src-gen/
+/*.yaml
+/*.json

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
-	path = gen_input/CoreDSL-Instruction-Set-Description
-	url = ../CoreDSL-Instruction-Set-Description.git

.project

@@ -23,6 +23,5 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

.settings/org.eclipse.cdt.codan.core.prefs

@@ -1,73 +0,0 @@
-eclipse.preferences.version=1
-org.eclipse.cdt.codan.checkers.errnoreturn=Warning
-org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false}
-org.eclipse.cdt.codan.checkers.errreturnvalue=Error
-org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"}
-org.eclipse.cdt.codan.checkers.nocommentinside=-Error
-org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"}
-org.eclipse.cdt.codan.checkers.nolinecomment=-Error
-org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"}
-org.eclipse.cdt.codan.checkers.noreturn=Error
-org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false}
-org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
-org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
-org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
-org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
-org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
-org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
-org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
-org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
-org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
-org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
-org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
-org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
-org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
-org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error
-org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
-org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
-org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
-org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
-org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
-org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
-org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
-org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
-org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
-org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
-org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
-org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
-org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
-org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
-org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
-org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
-org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
-org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
-org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
-org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
-org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
-org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
-org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
-org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
-org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
-org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
-org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
-org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}

.settings/org.eclipse.cdt.core.prefs

@@ -1,13 +0,0 @@
-eclipse.preferences.version=1
-environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
-environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/delimiter=\:
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/operation=append
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/value=/usr/lib/llvm-6.0
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/delimiter=\:
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/operation=append
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/value=/usr/lib/llvm-6.0
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
-environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -1,37 +0,0 @@
-eclipse.preferences.version=1
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/delimiter=\:
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/operation=remove
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
-environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true
-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/LIBRARY_PATH/delimiter=\:
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-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/delimiter=\:
-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/operation=remove
-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
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-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/operation=remove
-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
-environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

CMakeLists.txt

@@ -1,77 +1,121 @@
-cmake_minimum_required(VERSION 3.12)
+cmake_minimum_required(VERSION 3.18)
+list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
+
 # ##############################################################################
 #
 # ##############################################################################
 project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
+include(flink)
 
-find_package(elfio)
-
-if(WITH_LLVM)
-    if(DEFINED ENV{LLVM_HOME})
-        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
-    endif(DEFINED ENV{LLVM_HOME})
-    find_package(LLVM REQUIRED CONFIG)
-    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
-    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
-    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
-endif()
-
-#Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
-#set(CMAKE_MACOSX_RPATH ON)
-#set(CMAKE_SKIP_BUILD_RPATH FALSE)
-#set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
-#set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
-#set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
+find_package(elfio QUIET)
+find_package(jsoncpp)
+find_package(Boost COMPONENTS coroutine REQUIRED)
 
 add_subdirectory(softfloat)
 
-# library files
-FILE(GLOB TGC_SOURCES
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp 
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp
-)
 set(LIB_SOURCES
+    src/iss/plugin/instruction_count.cpp
+    src/iss/arch/tgc5c.cpp
+    src/vm/interp/vm_tgc5c.cpp
     src/vm/fp_functions.cpp
-    src/plugin/instruction_count.cpp
-    src/plugin/cycle_estimate.cpp
-    ${TGC_SOURCES}
+    src/iss/semihosting/semihosting.cpp
 )
 
+if(WITH_TCC)
+    list(APPEND LIB_SOURCES
+        src/vm/tcc/vm_tgc5c.cpp
+    )
+endif()
+
 if(WITH_LLVM)
-  set(LIB_SOURCES ${LIB_SOURCES}
+    list(APPEND LIB_SOURCES
+        src/vm/llvm/vm_tgc5c.cpp
         src/vm/llvm/fp_impl.cpp
-    #src/vm/llvm/vm_tgf_b.cpp
-    #src/vm/llvm/vm_tgf_c.cpp
+    )
+endif()
+
+if(WITH_ASMJIT)
+    list(APPEND LIB_SOURCES
+        src/vm/asmjit/vm_tgc5c.cpp
+    )
+endif()
+
+# library files
+FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
+FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
+FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
+list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
+
+foreach(FILEPATH ${GEN_ISS_SOURCES})
+    get_filename_component(CORE ${FILEPATH} NAME_WE)
+    string(TOUPPER ${CORE} CORE)
+    list(APPEND LIB_DEFINES CORE_${CORE})
+endforeach()
+
+message(STATUS "Core defines are ${LIB_DEFINES}")
+
+if(WITH_LLVM)
+    FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
+endif()
+
+if(WITH_TCC)
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+endif()
+
+if(WITH_ASMJIT)
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+endif()
+
+if(TARGET yaml-cpp::yaml-cpp)
+    list(APPEND LIB_SOURCES
+        src/iss/plugin/cycle_estimate.cpp
+        src/iss/plugin/instruction_count.cpp
     )
 endif()
 
 # Define the library
-add_library(${PROJECT_NAME} ${LIB_SOURCES})
-# list code gen dependencies
-if(TARGET ${CORE_NAME}_cpp)
-    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
-endif()
+add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
 
 if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
     target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
-target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
-if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
-    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-else()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-core)
+
+target_include_directories(${PROJECT_NAME} PUBLIC src)
+target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
+
+target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
+
+# only re-export the include paths
+get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
+target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
+get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
+
+if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+    target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+endif()
+
+target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
+
+if(TARGET yaml-cpp::yaml-cpp)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
+    target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
+endif()
+
+if(WITH_LLVM)
+    find_package(LLVM)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
+    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
+
+    if(BUILD_SHARED_LIBS)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
     endif()
-if(TARGET CONAN_PKG::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
-elseif(TARGET elfio::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
-else()
-    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
 endif()
 
 set_target_properties(${PROJECT_NAME} PROPERTIES
@@ -92,27 +136,52 @@ install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
     FILES_MATCHING # install only matched files
     PATTERN "*.h" # select header files
 )
+install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
+
 # ##############################################################################
 #
 # ##############################################################################
+set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
 project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
-# This sets the include directory for the reference project. This is the -I flag in gcc.
-target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-if(WITH_LLVM)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-endif()
-# Links the target exe against the libraries
-target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
-if(TARGET Boost::program_options)
-    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options Boost::thread)
+
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
 else()
-    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY} ${BOOST_thread_LIBRARY})
+    FILE(GLOB TGC_SOURCES
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+    )
+    list(APPEND TGC_SOURCES ${GEN_SOURCES})
 endif()
+
+foreach(F IN LISTS TGC_SOURCES)
+    if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
+        string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
+        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    endif()
+endforeach()
+
+# if(WITH_LLVM)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+# endif()
+# if(WITH_TCC)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+# endif()
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
+
+if(TARGET Boost::program_options)
+    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
+endif()
+
 target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
+
 if(Tcmalloc_FOUND)
     target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)
@@ -126,31 +195,57 @@ install(TARGETS tgc-sim
     PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
     INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
 )
+
+if(BUILD_TESTING)
+    # ... CMake code to create tests ...
+    add_test(NAME tgc-sim-interp
+        COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
+
+    if(WITH_TCC)
+        add_test(NAME tgc-sim-tcc
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
+    endif()
+
+    if(WITH_LLVM)
+        add_test(NAME tgc-sim-llvm
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
+    endif()
+
+    if(WITH_ASMJIT)
+        add_test(NAME tgc-sim-asmjit
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
+    endif()
+endif()
+
 # ##############################################################################
 #
 # ##############################################################################
+if(TARGET scc-sysc)
     project(dbt-rise-tgc_sc VERSION 1.0.0)
-
-include(SystemCPackage)
-if(SystemC_FOUND)
-    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
+    set(LIB_SOURCES
+        src/sysc/core_complex.cpp
+        src/sysc/register_tgc_c.cpp
+    )
+    FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
+    list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
+    add_library(${PROJECT_NAME} ${LIB_SOURCES})
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
-    endif()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
-    if(WITH_LLVM)
-        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-    endif()
 
-	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+    foreach(F IN LISTS TGC_SOURCES)
+        if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
+            string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
+            string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+            target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+        endif()
+    endforeach()
+
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+
+    # if(WITH_LLVM)
+    # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    # endif()
+    set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES
         VERSION ${PROJECT_VERSION}
         FRAMEWORK FALSE
@@ -166,4 +261,3 @@ if(SystemC_FOUND)
         INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
     )
 endif()
-

cmake/flink.cmake

@@ -0,0 +1,35 @@
+# according to https://github.com/horance-liu/flink.cmake/tree/master
+# SPDX-License-Identifier: Apache-2.0
+
+include(CMakeParseArguments)
+
+function(target_do_force_link_libraries target visibility lib)
+  if(MSVC)
+    target_link_libraries(${target} ${visibility} "/WHOLEARCHIVE:${lib}")
+  elseif(APPLE)
+    target_link_libraries(${target} ${visibility} -Wl,-force_load ${lib})
+  else()
+    target_link_libraries(${target} ${visibility} -Wl,--whole-archive ${lib} -Wl,--no-whole-archive)
+  endif()
+endfunction()
+
+function(target_force_link_libraries target)
+  cmake_parse_arguments(FLINK
+    ""
+    ""
+    "PUBLIC;INTERFACE;PRIVATE"
+    ${ARGN}
+  )
+  
+  foreach(lib IN LISTS FLINK_PUBLIC)
+    target_do_force_link_libraries(${target} PUBLIC ${lib})
+  endforeach()
+
+  foreach(lib IN LISTS FLINK_INTERFACE)
+    target_do_force_link_libraries(${target} INTERFACE ${lib})
+  endforeach()
+  
+  foreach(lib IN LISTS FLINK_PRIVATE)
+    target_do_force_link_libraries(${target} PRIVATE ${lib})
+  endforeach()
+endfunction()

contrib/instr/.gitignore

@@ -0,0 +1 @@
+/*.yaml

contrib/instr/TGC5C_instr.yaml

@@ -0,0 +1,624 @@
+
+RVI: 
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+    mask: 0b00000000000000000000000001111111
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+    delay:   1
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contrib/pa/.gitignore

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+/results
+/cwr
+/*.xml

contrib/pa/README.md

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+# Notes
+
+* requires conan version 1.59
+* requires decent cmake version 3.23
+
+Setup for tcsh:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+setenv TGFS_INSTALL_ROOT `pwd`/install
+setenv COWAREHOME <your SNPS PA installation>
+setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
+source $COWAREHOME/SLS/linux/setup.csh pae
+setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
+setenv PATH $COWAREHOME/common/bin/:${PATH}
+setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
+setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib/pa
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
+
+Setup for bash:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+export TGFS_INSTALL_ROOT `pwd`/install
+module load tools/pa/T-2022.06
+export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
+export CC=$COWAREHOME/SLS/linux/common/bin/gcc
+export CXX=$COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib/pa
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```

contrib/pa/build.tcl

@@ -16,7 +16,7 @@ namespace eval Specification {
                 set libdir "${install_dir}/lib64"
                 set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
                 # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
             }
             default {
                puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"

contrib/pa/tgc_import.tcl

@@ -6,14 +6,11 @@ proc getScriptDirectory {} {
     set scriptFolder [file dirname $dispScriptFile]
     return $scriptFolder
 }
-if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
     set hardware /HARDWARE/HW/HW
-} else {
-    set hardware /HARDWARE
-}
 
 set scriptDir [getScriptDirectory]
 set top_design_name core_complex
+set encap_name sysc::tgfs::${top_design_name}
 set clocks clk_i
 set resets rst_i
 set model_prefix "i_"
@@ -28,7 +25,8 @@ set model_postfix ""
 ::pct::set_update_existing_encaps_flag true
 ::pct::set_dynamic_port_arrays_flag true
 ::pct::set_import_scml_properties_flag true
-::pct::load_modules --set-category modules tgc_import.cc
+::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
 
 # Set Port Protocols correctly
 set block ${top_design_name}
@@ -38,13 +36,15 @@ foreach clock ${clocks} {
 foreach reset ${resets} {
     ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
 }
-::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
 
 # Set compile settings and look
 set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
+::pct::set_bounds i_${top_design_name} 200 300 100 400
+::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
 
 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

contrib/pa/tgc_import_tb.tcl

@@ -0,0 +1,71 @@
+source tgc_import.tcl
+set hardware /HARDWARE/HW/HW
+set FW_name ${scriptDir}/hello.elf
+
+puts "instantiate testbench elements"
+::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
+::pct::set_bounds i_Memory_Generic 1000 300 100 100
+
+::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
+::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
+						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+::pct::set_bounds i_Bus 700 300 100 400
+::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
+::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
+::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
+::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
+::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
+
+puts "instantiating clock manager"
+set clock "Clk"
+::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
+::pct::set_bounds ${clock}_clock 100 100 100 100
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
+
+puts "instantiating reset manager"
+set reset "Rst"
+ ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+::pct::set_bounds ${reset}_reset 300 100 100 100
+
+puts "connecting reset/clock"
+::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
+::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
+::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
+::pct::add_ports_to_connection C_rst i_Bus/Rst
+
+puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
+::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
+::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
+::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
+::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+
+::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::create_simulation_build_config Debug
+::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+# add build settings and save design for next steps
+#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
+#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
+
+#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
+#::simulation::run_simulation Simulation
+
+#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
+#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
+#::pct::export_system "export"
+#::cd "export"
+#::scsh::open-project
+#::scsh::build
+#::scsh::elab sim
+::pct::save_system testbench.xml

gen_input/.gitignore

@@ -1 +1,2 @@
 /src-gen/
+/CoreDSL-Instruction-Set-Description

gen_input/TGC5C.core_desc

@@ -0,0 +1,13 @@
+import "ISA/RVI.core_desc"
+import "ISA/RVM.core_desc"
+import "ISA/RVC.core_desc"
+
+Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned int MARCHID_VAL = 0x80000003;
+    }
+}

gen_input/TGFS.core_desc

@@ -1,37 +0,0 @@
-import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
-
-Core TGC_B provides RV32I {
-	architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000000000100000000;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-	}
-}
-
-Core TGC_C provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-    }
-}
-
-Core TGC_D provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-    }
-}

gen_input/templates/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
+ * Copyright (C) 2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,32 +33,33 @@
 def getRegisterSizes(){
 	def regs = registers.collect{it.size}
 	regs[-1]=64 // correct for NEXT_PC
-	regs+=[32, 32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+	regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     return regs
 }
 %>
+// clang-format off
+#include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
 
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
 
 ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
 
 void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
@@ -70,7 +71,7 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
 }
-
+// clang-format on

gen_input/templates/CORENAME.h.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * Copyright (C) 2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,14 +30,12 @@
  *
  *******************************************************************************/
 <%
-import com.minres.coredsl.util.BigIntegerWithRadix
-
 def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 def getRegisterSizes(){
     def regs = registers.collect{nativeTypeSize(it.size)}
-    regs+=[32,32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     return regs
 }
 def getRegisterOffsets(){
@@ -57,15 +55,12 @@ def byteSize(int size){
     return 128;
 }
 def getCString(def val){
-    if(val instanceof BigIntegerWithRadix)
-        return ((BigIntegerWithRadix)val).toCString()
-    else
-        return val.toString()
+    return val.toString()+'ULL'
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
-
+// clang-format off
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -80,23 +75,18 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     constexpr static char const* const core_type = "${coreDef.name}";
     
-    static constexpr std::array<const char*, ${registers.size}> reg_names{
-        {"${registers.collect{it.name}.join('", "')}"}};
+    static constexpr std::array<const char*, ${registers.size()}> reg_names{
+        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
  
-    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
-        {"${registers.collect{it.alias}.join('", "')}"}};
+    static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
+        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
 
     enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
 
     constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
 
     enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS,
-        TRAP_STATE=NUM_REGS,
-        PENDING_TRAP,
-        ICOUNT,
-        CYCLE,
-        INSTRET
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     };
 
     using reg_t = uint${addrDataWidth}_t;
@@ -109,19 +99,19 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
+    static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
         {${getRegisterSizes().join(',')}}};
 
-    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
+    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
         {${getRegisterOffsets().join(',')}}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
     
-    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
+    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
     };
@@ -140,14 +130,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
     inline uint64_t get_icount() { return reg.icount; }
 
@@ -155,21 +137,13 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline uint64_t stop_code() { return interrupt_sim; }
 
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
     virtual phys_addr_t virt2phys(const iss::addr_t& addr);
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
 
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
-protected:
+
 #pragma pack(push, 1)
     struct ${coreDef.name}_regs {<%
         registers.each { reg -> if(reg.size>0) {%> 
@@ -179,7 +153,8 @@ protected:
         uint64_t icount = 0;
         uint64_t cycle = 0;
         uint64_t instret = 0;
-        uint32_t last_branch;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
     } reg;
 #pragma pack(pop)
     std::array<address_type, 4> addr_mode;
@@ -199,3 +174,4 @@ if(fcsr != null) {%>
 }
 }            
 #endif /* _${coreDef.name.toUpperCase()}_H_ */
+// clang-format on

gen_input/templates/CORENAME_cyles.txt.gtl

@@ -3,7 +3,10 @@
 		{
 			"name"  :   "${instr.name}",
 			"size"  :   ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+			"encoding": "${instr.encoding}",
+            "mask":     "${instr.mask}",
+			"branch":   ${instr.modifiesPC},
+			"delay" :   ${instr.isConditional?"[1,1]":"1"}
 		}<%}%>
 	]
 }

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -0,0 +1,21 @@
+<% def getInstructionGroups() {
+    def instrGroups = [:]
+    instructions.each {
+        def groupName = it['instruction'].eContainer().name
+        if(!instrGroups.containsKey(groupName)) {
+            instrGroups[groupName]=[]
+        }
+        instrGroups[groupName]+=it;
+    }
+    instrGroups
+}%><%int index = 0; getInstructionGroups().each{name, instrList -> %>
+${name}: <% instrList.each { %>
+  ${it.instruction.name}:
+    index: ${index++}
+    encoding: ${it.encoding}
+    mask: ${it.mask}<%if(it.attributes.size) {%>
+    attributes: ${it.attributes}<%}%>
+    size:   ${it.length}
+    branch:   ${it.modifiesPC}
+    delay:   ${it.isConditional?"[1,1]":"1"}<%}}%>
+

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -0,0 +1,131 @@
+/*******************************************************************************
+ * Copyright (C) 2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <sysc/iss_factory.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <sysc/sc_core_adapter.h>
+#include <sysc/core_complex.h>
+#include <array>
+<%
+def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
+%>
+namespace iss {
+namespace interp {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#if defined(WITH_LLVM)
+namespace llvm {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+#if defined(WITH_TCC)
+namespace tcc {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+#if defined(WITH_ASMJIT)
+namespace asmjit {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+}
+// clang-format on

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -0,0 +1,363 @@
+/*******************************************************************************
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/asmjit/vm_base.h>
+#include <asmjit/asmjit.h>
+#include <util/logging.h>
+#include <iss/instruction_decoder.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace asmjit {
+
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::asmjit;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super = typename iss::asmjit::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using mem_type_e = typename super::mem_type_e;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using super::get_ptr_for;
+    using super::get_reg_for;
+    using super::get_reg_for_Gp;
+    using super::load_reg_from_mem;
+    using super::load_reg_from_mem_Gp;
+    using super::write_reg_to_mem;
+    using super::gen_read_mem;
+    using super::gen_write_mem;
+    using super::gen_wait;
+    using super::gen_leave;
+    using super::gen_sync;
+   
+    using this_class = vm_impl<ARCH>;
+    using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
+
+    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
+    enum globals_e {TVAL = 0, GLOBALS_SIZE};
+    void gen_block_prologue(jit_holder& jh) override;
+    void gen_block_epilogue(jit_holder& jh) override;
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+
+    void gen_instr_prologue(jit_holder& jh);
+    void gen_instr_epilogue(jit_holder& jh);
+    inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
+    template <typename T, typename = std::enable_if_t<std::is_integral_v<T>>> void gen_set_tval(jit_holder& jh, T new_tval) ;
+    void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ;
+
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    } 
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct instruction_descriptor {
+        uint32_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate disass */
+            <%instr.disass.eachLine{%>
+            ${it}<%}%>
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
+        }
+        x86::Compiler& cc = jh.cc;
+        cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
+        gen_sync(jh, PRE_SYNC, ${idx});
+        mov(cc, jh.pc, pc.val);
+        gen_set_tval(jh, instr);
+        pc = pc+${instr.length/8};
+        mov(cc, jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        /*generate behavior*/
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        gen_sync(jh, POST_SYNC, ${idx});
+        gen_instr_epilogue(jh);
+    	return returnValue;        
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
+        x86::Compiler& cc = jh.cc;
+        if(this->disass_enabled){          
+            auto mnemonic = std::string("illegal_instruction");
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+        }
+        cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str());
+        gen_sync(jh, PRE_SYNC, instr_descr.size());
+        mov(cc, jh.pc, pc.val);
+        gen_set_tval(jh, instr);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        mov(cc, jh.next_pc, pc.val);
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        gen_raise(jh, 0, 2);
+        gen_sync(jh, POST_SYNC, instr_descr.size());
+        gen_instr_epilogue(jh);
+        return BRANCH;
+    }
+};
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
+        }
+        return std::move(g_instr_descr);
+    }()) {}
+
+template <typename ARCH>
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
+    enum {TRAP_ID=1<<16};
+    code_word_t instr = 0;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&instr;
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    auto res = this->core.read(paddr, 4, data);
+    if (res != iss::Ok)
+        throw trap_access(TRAP_ID, pc.val);
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
+        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    ++inst_cnt;
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
+    if (f == nullptr) 
+        f = &this_class::illegal_instruction;
+    return (this->*f)(pc, instr, jh);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_prologue");
+
+    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
+
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_epilogue");
+    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    cmp(cc, current_trap_state, 0);
+    cc.jne(jh.trap_entry);
+    cc.inc(get_ptr_for(jh, traits::ICOUNT));
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
+    jh.pc = load_reg_from_mem_Gp(jh, traits::PC);
+    jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC);
+    jh.globals.resize(GLOBALS_SIZE);
+    jh.globals[TVAL] = get_reg_Gp(jh.cc, 64, false);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
+    x86::Compiler& cc = jh.cc;
+    cc.comment("//gen_block_epilogue");
+    cc.ret(jh.next_pc);
+
+    cc.bind(jh.trap_entry);
+    this->write_back(jh);
+
+    x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+
+    x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
+    mov(cc, current_pc, get_ptr_for(jh, traits::PC));
+
+    cc.comment("//enter trap call;");
+    InvokeNode* call_enter_trap;
+    cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
+    call_enter_trap->setArg(0, jh.arch_if_ptr);
+    call_enter_trap->setArg(1, current_trap_state);
+    call_enter_trap->setArg(2, current_pc);
+    call_enter_trap->setArg(3, jh.globals[TVAL]);
+
+    x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC);
+    mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
+    mov(cc, jh.next_pc, current_next_pc);
+
+    mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
+    cc.ret(jh.next_pc);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
+    auto& cc = jh.cc;
+    cc.comment("//gen_raise");
+    auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
+    mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
+}
+template <typename ARCH>
+template <typename T, typename>
+void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, T new_tval) {
+        mov(jh.cc, jh.globals[TVAL], new_tval);
+    }
+template <typename ARCH>
+void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) {
+    if(std::holds_alternative<x86::Gp>(_new_tval)) {
+        x86::Gp new_tval = std::get<x86::Gp>(_new_tval);
+        if(new_tval.size() < 8)
+            new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false);
+        mov(jh.cc, jh.globals[TVAL], new_tval);
+    } else {
+        throw std::runtime_error("Variant not supported in gen_set_tval");
+    }
+}
+
+} // namespace tgc5c
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace asmjit
+} // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,16 +29,27 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
-#include "../fp_functions.h"
+<%
+def nativeTypeSize(int size){
+    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
+}
+%>
+// clang-format off
+#include <cstdint>
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
+#include <vm/fp_functions.h>
 #include <util/logging.h>
+#include <boost/coroutine2/all.hpp>
+#include <functional>
+#include <exception>
+#include <vector>
 #include <sstream>
+#include <iss/instruction_decoder.h>
+
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -53,6 +64,11 @@ namespace interp {
 namespace ${coreDef.name.toLowerCase()} {
 using namespace iss::arch;
 using namespace iss::debugger;
+using namespace std::placeholders;
+
+struct memory_access_exception : public std::exception{
+    memory_access_exception(){}
+};
 
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
@@ -64,6 +80,7 @@ public:
     using addr_t      = typename super::addr_t;
     using reg_t       = typename traits::reg_t;
     using mem_type_e  = typename traits::mem_type_e;
+    using opcode_e    = typename traits::opcode_e;
     
     vm_impl();
 
@@ -84,33 +101,19 @@ protected:
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+<%
+def fcsr = registers.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}     
+<%}%>
 
-    compile_func decode_inst(code_word_t instr) ;
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
-
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        compile_func opc;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+        this->core.reg.trap_state = trap_val;
     }
 
     inline void leave(unsigned lvl){
@@ -121,44 +124,17 @@ protected:
         this->core.wait_until(type);
     }
 
-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-    }
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-    }
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-    }
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    inline void set_tval(uint64_t new_tval){
+        tval = new_tval;
     }
+
+    uint64_t fetch_count{0};
+    uint64_t tval{0};
+
+    using yield_t = boost::coroutines2::coroutine<void>::push_type;
+    using coro_t = boost::coroutines2::coroutine<void>::pull_type;
+    std::vector<coro_t> spawn_blocks;
+
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -166,93 +142,55 @@ protected:
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
     
+    inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
+        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
+             if(*it){
+                 (*it)();
+                 ++it;
+             } else
+                 spawn_blocks.erase(it);
+    }
+<%functions.each{ it.eachLine { %>
+    ${it}<%}%>
+<%}%>
+
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
+    struct instruction_descriptor {
+        uint32_t length;
         uint32_t value;
         uint32_t mask;
-        compile_func op;
+        typename arch::traits<ARCH>::opcode_e op;
     };
 
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
     }};
 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *PC=*NEXT_PC;
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */
-            <%instr.disass.eachLine{%>${it}
-            <%}%>
-        }
-        // used registers<%instr.usedVariables.each{ k,v->
-            if(v.isArray) {%>
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-        <%}}%>// calculate next pc value
-        *NEXT_PC = *PC + ${instr.length/8};
-        // execute instruction
-        try {
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>} catch(...){}
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-        raise(0,  2);
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        }
-        pc.val=*NEXT_PC;
-        return pc;
-    }
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
 
-    static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        auto phys_pc = this->core.v2p(pc);
+        if(this->core.has_mmu()) {
+            auto phys_pc = this->core.virt2phys(pc);
 //            if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
 //                if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
 //                if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
+//                    if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
+//                        return iss::Err;
 //            } else {
-            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
+                if (this->core.read(phys_pc, 4, data) != iss::Ok)
+                    return iss::Err;
 //            }
+        } else {
+            if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
+                return iss::Err;
+
+        }
         return iss::Ok;
     }
 };
@@ -280,20 +218,23 @@ constexpr size_t bit_count(uint32_t u) {
 
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    for (auto instr : instr_descr) {
-        auto quadrant = instr.value & 0x3;
-        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-    }
-    for(auto& lut: qlut){
-        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
-            return bit_count(a.mask) > bit_count(b.mask);
-        });
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
         }
+        return std::move(g_instr_descr);
+    }()) {}
+
+inline bool is_icount_limit_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
 }
 
-inline bool is_count_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
+inline bool is_fcount_limit_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
 }
 
 inline bool is_jump_to_self_enabled(finish_cond_e cond){
@@ -301,36 +242,84 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
 }
 
 template <typename ARCH>
-typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
-    for(auto& e: qlut[instr&0x3]){
-        if(!((instr&e.mask) ^ e.value )) return e.opc;
-    }
-    return &this_class::illegal_intruction;
-}
-
-template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
-    // we fetch at max 4 byte, alignment is 2
-    code_word_t insn = 0;
-    auto *const data = (uint8_t *)&insn;
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
     auto pc=start;
+    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto& trap_state = this->core.reg.trap_state;
+    auto& icount =  this->core.reg.icount;
+    auto& cycle =  this->core.reg.cycle;
+    auto& instret =  this->core.reg.instret;
+    auto& instr =  this->core.reg.instruction;
+    // we fetch at max 4 byte, alignment is 2
+    auto *const data = reinterpret_cast<uint8_t*>(&instr);
+
     while(!this->core.should_stop() &&
-            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
-        auto res = fetch_ins(pc, data);
-        if(res!=iss::Ok){
+            !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
+            !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
+        fetch_count++;
+        if(fetch_ins(pc, data)!=iss::Ok){
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
-                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto f = decode_inst(insn);
-            pc = (this->*f)(pc, insn);
+                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            uint32_t inst_index = instr_decoder.decode_instr(instr);
+            opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
+            if(inst_index <instr_descr.size())
+                inst_id = instr_descr.at(instr_decoder.decode_instr(instr)).op;
+
+            // pre execution stuff
+            this->core.reg.last_branch = 0;
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            try{
+                switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
+                case arch::traits<ARCH>::opcode_e::${instr.name}: {
+                    <%instr.fields.eachLine{%>${it}
+                    <%}%>if(this->disass_enabled){
+                        /* generate console output when executing the command */<%instr.disass.eachLine{%>
+                        ${it}<%}%>
+                    }
+                    // used registers<%instr.usedVariables.each{ k,v->
+                    if(v.isArray) {%>
+                    auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+                    auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+                    <%}}%>// calculate next pc value
+                    *NEXT_PC = *PC + ${instr.length/8};
+                    // execute instruction<%instr.behavior.eachLine{%>
+                    ${it}<%}%>
+                    break;
+                }// @suppress("No break at end of case")<%}%>
+                default: {
+                    *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+                    raise(0,  2);
+                }
+                }
+            }catch(memory_access_exception& e){}
+            // post execution stuff
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
+            // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.reg.trap_state =  this->core.reg.pending_trap;
+            // trap check
+            if(trap_state!=0){
+                //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
+                auto mcause = (trap_state>>16) & 0xff; 
+                super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
+            } else {
+                icount++;
+                instret++;
+            }
+            cycle++;
+            pc.val=*NEXT_PC;
+            this->core.reg.PC = this->core.reg.NEXT_PC;
+            this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
     }
     return pc;
 }
 
-} // namespace mnrv32
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -340,3 +329,34 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 }
 } // namespace interp
 } // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -0,0 +1,386 @@
+/*******************************************************************************
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/llvm/vm_base.h>
+#include <util/logging.h>
+#include <iss/instruction_decoder.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace llvm {
+namespace fp_impl {
+void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
+}
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::llvm;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super = typename iss::llvm::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using vm_base<ARCH>::get_reg_ptr;
+
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+
+    template <typename T> inline ConstantInt *size(T type) {
+        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
+    }
+
+    void setup_module(Module* m) override {
+        super::setup_module(m);
+        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
+    }
+
+    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
+        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
+    }
+
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
+
+    void gen_leave_behavior(BasicBlock *leave_blk) override;
+    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
+    void gen_leave_trap(unsigned lvl);
+    void gen_wait(unsigned type);
+    void set_tval(uint64_t new_tval);
+    void set_tval(Value* new_tval);
+    void gen_trap_behavior(BasicBlock *) override;
+    void gen_instr_prologue();
+    void gen_instr_epilogue(BasicBlock *bb);
+
+    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
+        return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
+    }
+
+    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
+                                                           this->get_type(traits::XLEN));
+        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
+    }
+
+    // some compile time constants
+
+    using this_class = vm_impl<ARCH>;
+    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
+                                                                                  code_word_t instr,
+                                                                                  BasicBlock *bb);
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    }   
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct instruction_descriptor {
+        uint32_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
+            ${it}<%}%>
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,${idx});
+        
+        this->gen_set_pc(pc, traits::PC);
+        this->set_tval(instr);
+        pc=pc+ ${instr.length/8};
+        this->gen_set_pc(pc, traits::NEXT_PC);
+        
+        this->gen_instr_prologue();
+        /*generate behavior*/
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        this->gen_sync(POST_SYNC, ${idx});
+        this->gen_instr_epilogue(bb);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
+        if(this->disass_enabled){
+            auto mnemonic = std::string("illegal_instruction");
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
+                                   get_reg_ptr(traits::PC), true);
+        this->builder.CreateStore(
+            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
+                                     this->gen_const(64U, 1)),
+            get_reg_ptr(traits::ICOUNT), true);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        this->set_tval(instr);
+        this->gen_raise_trap(0, 2);     // illegal instruction trap
+		this->gen_sync(iss::POST_SYNC, instr_descr.size());
+        bb = this->leave_blk;
+        this->gen_instr_epilogue(bb);
+        this->builder.CreateBr(bb);
+        return std::make_tuple(BRANCH, nullptr);
+    }    
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+    volatile CODE_WORD x = instr;
+    instr = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
+        }
+        return std::move(g_instr_descr);
+    }()) {}
+
+template <typename ARCH>
+std::tuple<continuation_e, BasicBlock *>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
+    // we fetch at max 4 byte, alignment is 2
+    enum {TRAP_ID=1<<16};
+    code_word_t instr = 0;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&instr;
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    //TODO: re-add page handling
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+    auto res = this->core.read(paddr, 4, data);
+    if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//    }
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    // curr pc on stack
+    ++inst_cnt;
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
+    if (f == nullptr) {
+        f = &this_class::illegal_instruction;
+    }
+    return (this->*f)(pc, instr, this_block);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
+    this->builder.SetInsertPoint(leave_blk);
+    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
+    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
+    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
+    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
+    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_wait(unsigned type) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
+    this->builder.CreateCall(this->mod->getFunction("wait"), args);
+}
+
+template <typename ARCH>
+inline void vm_impl<ARCH>::set_tval(uint64_t tval) {
+    auto tmp_tval = this->gen_const(64, tval);
+    this->set_tval(tmp_tval);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
+    this->builder.CreateStore(this->gen_ext(new_tval, 64, false), this->tval);
+}
+template <typename ARCH> 
+void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
+    this->builder.SetInsertPoint(trap_blk);
+    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    auto *cur_pc_val = this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), true);
+    std::vector<Value *> args{this->core_ptr,
+                                this->adj_to64(trap_state_val),
+                                this->adj_to64(cur_pc_val),
+                              this->adj_to64(this->builder.CreateLoad(this->get_type(64),this->tval))};
+    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
+    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
+
+    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
+    this->builder.CreateRet(trap_addr_val);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue() {
+    auto* trap_val =
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PENDING_TRAP), get_reg_ptr(arch::traits<ARCH>::PENDING_TRAP));
+    this->builder.CreateStore(trap_val, get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), false);
+}
+            
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
+    auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
+    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    this->gen_cond_branch(this->builder.CreateICmp(
+                              ICmpInst::ICMP_EQ, v,
+                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
+                          target_bb, this->trap_blk, 1);
+    this->builder.SetInsertPoint(target_bb);
+    // update icount
+    auto* icount_val = this->builder.CreateAdd(
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
+    this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
+}
+
+} // namespace ${coreDef.name.toLowerCase()}
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace llvm
+} // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/llvm/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/llvm/incl-CORENAME.h.gtl

@@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/llvm/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -1,325 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/llvm/vm_base.h>
-#include <util/logging.h>
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace llvm {
-namespace fp_impl {
-void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
-}
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::llvm;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
-public:
-    using super = typename iss::llvm::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using vm_base<ARCH>::get_reg_ptr;
-
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
-
-    template <typename T> inline ConstantInt *size(T type) {
-        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
-    }
-
-    void setup_module(Module* m) override {
-        super::setup_module(m);
-        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
-    }
-
-    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
-        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
-    }
-
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
-
-    void gen_leave_behavior(BasicBlock *leave_blk) override;
-
-    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
-
-    void gen_leave_trap(unsigned lvl);
-
-    void gen_wait(unsigned type);
-
-    void gen_trap_behavior(BasicBlock *) override;
-
-    void gen_trap_check(BasicBlock *bb);
-
-    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
-        return this->builder.CreateLoad(get_reg_ptr(i), false);
-    }
-
-    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
-                                                           this->get_type(traits<ARCH>::XLEN));
-        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
-    }
-
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
-
-    using this_class = vm_impl<ARCH>;
-    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
-                                                                                  code_word_t instr,
-                                                                                  BasicBlock *bb);
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-	std::array<compile_func *, 4> qlut;
-
-	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
-    }
-
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
-    	${it}<%}%>
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
-		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
-                                   get_reg_ptr(traits<ARCH>::PC), true);
-        this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
-                                     this->gen_const(64U, 1)),
-            get_reg_ptr(traits<ARCH>::ICOUNT), true);
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        this->gen_raise_trap(0, 2);     // illegal instruction trap
-		this->gen_sync(iss::POST_SYNC, instr_descr.size());
-        this->gen_trap_check(this->leave_blk);
-        return std::make_tuple(BRANCH, nullptr);
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
-    }
-}
-
-template <typename ARCH>
-std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&insn;
-    paddr = this->core.v2p(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        auto res = this->core.read(paddr, 2, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-        }
-    } else {
-        auto res = this->core.read(paddr, 4, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
-    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-    // curr pc on stack
-    ++inst_cnt;
-    auto lut_val = extract_fields(insn);
-    auto f = qlut[insn & 0x3][lut_val];
-    if (f == nullptr) {
-        f = &this_class::illegal_intruction;
-    }
-    return (this->*f)(pc, insn, this_block);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
-    this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
-    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
-    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
-    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
-    this->builder.CreateCall(this->mod->getFunction("wait"), args);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
-    this->builder.SetInsertPoint(trap_blk);
-    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
-                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
-    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateRet(trap_addr_val);
-}
-
-template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
-    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
-    this->gen_cond_branch(this->builder.CreateICmp(
-                              ICmpInst::ICMP_EQ, v,
-                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-                          bb, this->trap_blk, 1);
-}
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace llvm
-} // namespace iss

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2020 MINRES Technologies GmbH
+ * Copyright (C) 2020-2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,15 +29,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/tcc/vm_base.h>
 #include <util/logging.h>
 #include <sstream>
+#include <iss/instruction_decoder.h>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -55,10 +55,12 @@ using namespace iss::debugger;
 
 template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
 public:
+    using traits = arch::traits<ARCH>;
     using super       = typename iss::tcc::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
     using code_word_t = typename super::code_word_t;
+    using mem_type_e  = typename traits::mem_type_e;    
     using addr_t      = typename super::addr_t;
     using tu_builder  = typename super::tu_builder;
 
@@ -82,7 +84,7 @@ protected:
     using compile_ret_t = std::tuple<continuation_e>;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
     void setup_module(std::string m) override {
         super::setup_module(m);
@@ -98,16 +100,20 @@ protected:
 
     void gen_wait(tu_builder& tu, unsigned type);
 
+    inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
+
+    inline void gen_set_tval(tu_builder& tu, value new_tval);
+
     inline void gen_trap_check(tu_builder& tu) {
         tu("if(*trap_state!=0) goto trap_entry;");
     }
 
     inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
         switch(reg_num){
-        case traits<ARCH>::NEXT_PC:
+        case traits::NEXT_PC:
             tu("*next_pc = {:#x};", pc.val);
             break;
-        case traits<ARCH>::PC:
+        case traits::PC:
             tu("*pc = {:#x};", pc.val);
             break;
         default:
@@ -119,167 +125,158 @@ protected:
         }
     }
 
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
     
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    std::array<compile_func *, 4> qlut;
-
-    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
 
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
+    struct instruction_descriptor {
+        uint32_t length;
         uint32_t value;
         uint32_t mask;
         compile_func op;
     };
 
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
 
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
+        tu("${instr.name}_{:#010x}:", pc.val);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
             ${it}<%}%>
         }
+        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
+        pc=pc+ ${instr.length/8};
+        gen_set_pc(tu, pc, traits::NEXT_PC);
+        tu.open_scope();
+        this->gen_set_tval(tu, instr);
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        tu.close_scope();
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
+        gen_trap_check(tu);        
+        return returnValue;
+    }
     <%}%>
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t illegal_instruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
         vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
+        }
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         gen_raise_trap(tu, 0, 2);     // illegal instruction trap
+        this->gen_set_tval(tu, instr);
         vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
         vm_impl::gen_trap_check(tu);
         return BRANCH;
     }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
+template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+    volatile CODE_WORD x = instr;
+    instr = 2 * x;
 }
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
-    }
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
         }
+        return std::move(g_instr_descr);
+    }()) {}
 
 template <typename ARCH>
 std::tuple<continuation_e>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    code_word_t instr = 0;
     phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&insn;
-    paddr = this->core.v2p(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        auto res = this->core.read(paddr, 2, data);
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    //TODO: re-add page handling
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+    auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
     if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-        }
-    } else {
-        auto res = this->core.read(paddr, 4, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
-    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+//    }
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
-    auto lut_val = extract_fields(insn);
-    auto f = qlut[insn & 0x3][lut_val];
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
     if (f == nullptr) {
-        f = &this_class::illegal_intruction;
+        f = &this_class::illegal_instruction;
     }
-    return (this->*f)(pc, insn, tu);
+    return (this->*f)(pc, instr, tu);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
-    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+    tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
+    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
 }
 
+template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
+    tu(fmt::format("tval = {};", new_tval));
+}
+template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, value new_tval) {
+    tu(fmt::format("tval = {};", new_tval.str));
+}
+
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    tu("enter_trap(core_ptr, *trap_state, *pc);");
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
+    this->gen_sync(tu, POST_SYNC, -1);    
+    tu("enter_trap(core_ptr, *trap_state, *pc, tval);");
+    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
     tu("return *next_pc;");
 }
 
-} // namespace mnrv32
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -287,5 +284,36 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-}
+} // namesapce tcc
 } // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/tcc/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/tcc/incl-CORENAME.h.gtl

@@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/tcc/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

incl/iss/arch/.gitignore

@@ -1 +0,0 @@
-/tgc_*.h

incl/iss/arch/riscv_hart_m_p.h

@@ -1,976 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial implementation
- ******************************************************************************/
-
-#ifndef _RISCV_HART_M_P_H
-#define _RISCV_HART_M_P_H
-
-#include "riscv_hart_common.h"
-#include "iss/arch/traits.h"
-#include "iss/instrumentation_if.h"
-#include "iss/log_categories.h"
-#include "iss/vm_if.h"
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <array>
-#include <elfio/elfio.hpp>
-#include <fmt/format.h>
-#include <iomanip>
-#include <sstream>
-#include <type_traits>
-#include <unordered_map>
-#include <functional>
-#include <util/bit_field.h>
-#include <util/ities.h>
-#include <util/sparse_array.h>
-
-#if defined(__GNUC__)
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-#else
-#define likely(x) x
-#define unlikely(x) x
-#endif
-
-namespace iss {
-namespace arch {
-
-template <typename BASE> class riscv_hart_m_p : public BASE {
-protected:
-    const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-    const std::array<const char *, 16> trap_str = {{""
-                                              "Instruction address misaligned", // 0
-                                              "Instruction access fault",       // 1
-                                              "Illegal instruction",            // 2
-                                              "Breakpoint",                     // 3
-                                              "Load address misaligned",        // 4
-                                              "Load access fault",              // 5
-                                              "Store/AMO address misaligned",   // 6
-                                              "Store/AMO access fault",         // 7
-                                              "Environment call from U-mode",   // 8
-                                              "Environment call from S-mode",   // 9
-                                              "Reserved",                       // a
-                                              "Environment call from M-mode",   // b
-                                              "Instruction page fault",         // c
-                                              "Load page fault",                // d
-                                              "Reserved",                       // e
-                                              "Store/AMO page fault"}};
-    const std::array<const char *, 12> irq_str = {
-        {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-         "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-         "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-public:
-    using core = BASE;
-    using this_class = riscv_hart_m_p<BASE>;
-    using phys_addr_t = typename core::phys_addr_t;
-    using reg_t = typename core::reg_t;
-    using addr_t = typename core::addr_t;
-
-    using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
-    using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
-
-    // primary template
-    template <class T, class Enable = void> struct hart_state {};
-    // specialization 32bit
-    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
-    public:
-        BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        BF_FIELD(SD, 31, 1);
-        // Trap SRET
-        BF_FIELD(TSR, 22, 1);
-        // Timeout Wait
-        BF_FIELD(TW, 21, 1);
-        // Trap Virtual Memory
-        BF_FIELD(TVM, 20, 1);
-        // Make eXecutable Readable
-        BF_FIELD(MXR, 19, 1);
-        // permit Supervisor User Memory access
-        BF_FIELD(SUM, 18, 1);
-        // Modify PRiVilege
-        BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        BF_FIELD(XS, 15, 2);
-        // floating-point unit status Off/Initial/Clean/Dirty
-        BF_FIELD(FS, 13, 2);
-        // machine previous privilege
-        BF_FIELD(MPP, 11, 2);
-        // supervisor previous privilege
-        BF_FIELD(SPP, 8, 1);
-        // previous machine interrupt-enable
-        BF_FIELD(MPIE, 7, 1);
-        // previous supervisor interrupt-enable
-        BF_FIELD(SPIE, 5, 1);
-        // previous user interrupt-enable
-        BF_FIELD(UPIE, 4, 1);
-        // machine interrupt-enable
-        BF_FIELD(MIE, 3, 1);
-        // supervisor interrupt-enable
-        BF_FIELD(SIE, 1, 1);
-        // user interrupt-enable
-        BF_FIELD(UIE, 0, 1);
-        END_BF_DECL();
-
-        mstatus_t mstatus;
-
-        static const reg_t mstatus_reset_val = 0x1800;
-
-        void write_mstatus(T val) {
-            auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
-            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
-            mstatus = new_val;
-        }
-
-        static constexpr uint32_t get_mask() {
-            //return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000  // only machine mode is supported
-            //       +-SD
-            //       |        +-TSR
-            //       |        |+-TW
-            //       |        ||+-TVM
-            //       |        |||+-MXR
-            //       |        ||||+-SUM
-            //       |        |||||+-MPRV
-            //       |        |||||| +-XS
-            //       |        |||||| | +-FS
-            //       |        |||||| | | +-MPP
-            //       |        |||||| | | |  +-SPP
-            //       |        |||||| | | |  |+-MPIE
-            //       |        ||||||/|/|/|  ||   +-MIE
-            return 0b00000000000000000001100010001000;
-        }
-    };
-    using hart_state_type = hart_state<reg_t>;
-
-    constexpr reg_t get_irq_mask() {
-        return 0b100010001000; // only machine mode is supported
-    }
-
-    constexpr reg_t get_pc_mask() {
-        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
-    }
-
-    riscv_hart_m_p();
-    virtual ~riscv_hart_m_p() = default;
-
-    void reset(uint64_t address) override;
-
-    std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
-
-    iss::status read(const address_type type, const access_type access, const uint32_t space,
-            const uint64_t addr, const unsigned length, uint8_t *const data) override;
-    iss::status write(const address_type type, const access_type access, const uint32_t space,
-            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
-
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
-
-    const reg_t& get_mhartid() const { return mhartid_reg;	}
-	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
-                pc, instr, (reg_t)state.mstatus, this->reg.icount);
-    };
-
-    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
-
-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
-    void set_csr(unsigned addr, reg_t val){
-        csr[addr & csr.page_addr_mask] = val;
-    }
-
-protected:
-    struct riscv_instrumentation_if : public iss::instrumentation_if {
-
-        riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
-        : arch(arch) {}
-        /**
-         * get the name of this architecture
-         *
-         * @return the name of this architecture
-         */
-        const std::string core_type_name() const override { return traits<BASE>::core_type; }
-
-        virtual uint64_t get_pc() { return arch.get_pc(); };
-
-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
-
-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
-
-        riscv_hart_m_p<BASE> &arch;
-    };
-
-    friend struct riscv_instrumentation_if;
-    addr_t get_pc() { return this->reg.PC; }
-    addr_t get_next_pc() { return this->reg.NEXT_PC; }
-
-    virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
-    virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
-
-    virtual iss::status read_csr(unsigned addr, reg_t &val);
-    virtual iss::status write_csr(unsigned addr, reg_t val);
-
-    hart_state_type state;
-    int64_t cycle_offset{0};
-    uint64_t mcycle_csr{0};
-    int64_t instret_offset{0};
-    uint64_t minstret_csr{0};
-    reg_t fault_data;
-    uint64_t tohost = tohost_dflt;
-    uint64_t fromhost = fromhost_dflt;
-    unsigned to_host_wr_cnt = 0;
-    riscv_instrumentation_if instr_if;
-
-    using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
-    using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
-    using csr_page_type = typename csr_type::page_type;
-    mem_type mem;
-    csr_type csr;
-    std::stringstream uart_buf;
-    std::unordered_map<reg_t, uint64_t> ptw;
-    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
-    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
-    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
-
-private:
-    iss::status read_reg(unsigned addr, reg_t &val);
-    iss::status write_reg(unsigned addr, reg_t val);
-    iss::status read_null(unsigned addr, reg_t &val);
-    iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
-    iss::status read_cycle(unsigned addr, reg_t &val);
-    iss::status write_cycle(unsigned addr, reg_t val);
-    iss::status read_instret(unsigned addr, reg_t &val);
-    iss::status write_instret(unsigned addr, reg_t val);
-    iss::status read_tvec(unsigned addr, reg_t &val);
-    iss::status read_time(unsigned addr, reg_t &val);
-    iss::status read_status(unsigned addr, reg_t &val);
-    iss::status write_status(unsigned addr, reg_t val);
-    iss::status write_cause(unsigned addr, reg_t val);
-    iss::status read_ie(unsigned addr, reg_t &val);
-    iss::status write_ie(unsigned addr, reg_t val);
-    iss::status read_ip(unsigned addr, reg_t &val);
-    iss::status write_ip(unsigned addr, reg_t val);
-    iss::status read_hartid(unsigned addr, reg_t &val);
-    iss::status write_epc(unsigned addr, reg_t val);
-
-    reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
-
-protected:
-    void check_interrupt();
-};
-
-template <typename BASE>
-riscv_hart_m_p<BASE>::riscv_hart_m_p()
-: state()
-, instr_if(*this) {
-    // reset values
-    csr[misa] = traits<BASE>::MISA_VAL;
-    csr[mvendorid] = 0x669;
-    csr[marchid] = 0x80000003;
-    csr[mimpid] = 1;
-
-    uart_buf.str("");
-    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-    }
-    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        //csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    // common regs
-    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
-    for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_reg;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    // special handling & overrides
-    csr_rd_cb[time] = &this_class::read_time;
-    csr_rd_cb[timeh] = &this_class::read_time;
-    csr_rd_cb[cycle] = &this_class::read_cycle;
-    csr_rd_cb[cycleh] = &this_class::read_cycle;
-    csr_rd_cb[instret] = &this_class::read_instret;
-    csr_rd_cb[instreth] = &this_class::read_instret;
-
-    csr_rd_cb[mcycle] = &this_class::read_cycle;
-    csr_wr_cb[mcycle] = &this_class::write_cycle;
-    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_wr_cb[mcycleh] = &this_class::write_cycle;
-    csr_rd_cb[minstret] = &this_class::read_instret;
-    csr_wr_cb[minstret] = &this_class::write_instret;
-    csr_rd_cb[minstreth] = &this_class::read_instret;
-    csr_wr_cb[minstreth] = &this_class::write_instret;
-    csr_rd_cb[mstatus] = &this_class::read_status;
-    csr_wr_cb[mstatus] = &this_class::write_status;
-    csr_wr_cb[mcause] = &this_class::write_cause;
-    csr_rd_cb[mtvec] = &this_class::read_tvec;
-    csr_wr_cb[mepc] = &this_class::write_epc;
-    csr_rd_cb[mip] = &this_class::read_ip;
-    csr_wr_cb[mip] = &this_class::write_ip;
-    csr_rd_cb[mie] = &this_class::read_ie;
-    csr_wr_cb[mie] = &this_class::write_ie;
-    csr_rd_cb[mhartid] = &this_class::read_hartid;
-    csr_rd_cb[mcounteren] = &this_class::read_null;
-    csr_wr_cb[mcounteren] = &this_class::write_null;
-    csr_wr_cb[misa] = &this_class::write_null;
-    csr_wr_cb[mvendorid] = &this_class::write_null;
-    csr_wr_cb[marchid] = &this_class::write_null;
-    csr_wr_cb[mimpid] = &this_class::write_null;
-}
-
-template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
-    FILE *fp = fopen(name.c_str(), "r");
-    if (fp) {
-        std::array<char, 5> buf;
-        auto n = fread(buf.data(), 1, 4, fp);
-        if (n != 4) throw std::runtime_error("input file has insufficient size");
-        buf[4] = 0;
-        if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
-            // Create elfio reader
-            ELFIO::elfio reader;
-            // Load ELF data
-            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
-            // check elf properties
-            if (reader.get_class() != ELFCLASS32)
-                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
-            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
-            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
-            auto entry = reader.get_entry();
-            for (const auto pseg : reader.segments) {
-                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
-                const auto seg_data = pseg->get_data();
-                if (fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
-                            traits<BASE>::MEM, pseg->get_physical_address(),
-                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
-                    if (res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
-                                   << pseg->get_physical_address();
-                }
-            }
-            for(const auto sec : reader.sections) {
-                if(sec->get_name() == ".symtab") {
-                    if ( SHT_SYMTAB == sec->get_type() ||
-                            SHT_DYNSYM == sec->get_type() ) {
-                        ELFIO::symbol_section_accessor symbols( reader, sec );
-                        auto sym_no = symbols.get_symbols_num();
-                        std::string   name;
-                        ELFIO::Elf64_Addr    value   = 0;
-                        ELFIO::Elf_Xword     size    = 0;
-                        unsigned char bind    = 0;
-                        unsigned char type    = 0;
-                        ELFIO::Elf_Half      section = 0;
-                        unsigned char other   = 0;
-                        for ( auto i = 0U; i < sym_no; ++i ) {
-                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
-                            if(name=="tohost") {
-                                tohost = value;
-                            } else if(name=="fromhost") {
-                                fromhost = value;
-                            }
-                        }
-                    }
-                } else if (sec->get_name() == ".tohost") {
-                    tohost = sec->get_address();
-                    fromhost = tohost + 0x40;
-                }
-
-            }
-            return std::make_pair(entry, true);
-        }
-        throw std::runtime_error("memory load file is not a valid elf file");
-    }
-    throw std::runtime_error("memory load file not found");
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
-        const uint64_t addr, const unsigned length, uint8_t *const data) {
-#ifndef NDEBUG
-    if (access && iss::access_type::DEBUG) {
-        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
-    } else if(access && iss::access_type::FETCH){
-        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
-    } else {
-        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
-   }
-#endif
-    try {
-        switch (space) {
-        case traits<BASE>::MEM: {
-            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
-                fault_data = addr;
-                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
-                if(alignment>1 && (addr&(alignment-1))){
-                    this->reg.trap_state = 1<<31 | 4<<16;
-                    fault_data=addr;
-                    return iss::Err;
-                }
-                auto res = type==iss::address_type::PHYSICAL?
-                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
-                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)){
-                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
-                    fault_data=addr;
-                }
-                return res;
-            } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
-                fault_data=ta.addr;
-                return iss::Err;
-            }
-        } break;
-        case traits<BASE>::CSR: {
-            if (length != sizeof(reg_t)) return iss::Err;
-            return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
-        } break;
-        case traits<BASE>::FENCE: {
-            if ((addr + length) > mem.size()) return iss::Err;
-            return iss::Ok;
-        } break;
-        case traits<BASE>::RES: {
-            auto it = atomic_reservation.find(addr);
-            if (it != atomic_reservation.end() && it->second != 0) {
-                memset(data, 0xff, length);
-                atomic_reservation.erase(addr);
-            } else
-                memset(data, 0, length);
-        } break;
-        default:
-            return iss::Err; // assert("Not supported");
-        }
-        return iss::Ok;
-    } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
-        fault_data=ta.addr;
-        return iss::Err;
-    }
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
-        const uint64_t addr, const unsigned length, const uint8_t *const data) {
-#ifndef NDEBUG
-    const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
-    switch (length) {
-    case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    default:
-        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
-    }
-#endif
-    try {
-        switch (space) {
-        case traits<BASE>::MEM: {
-            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
-                fault_data = addr;
-                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                if(!(access && iss::access_type::DEBUG) &&  length>1 && (addr&(length-1))){
-                    this->reg.trap_state = 1<<31 | 6<<16;
-                    fault_data=addr;
-                    return iss::Err;
-                }
-                auto res = type==iss::address_type::PHYSICAL?
-                        write_mem(phys_addr_t{access, space, addr}, length, data):
-                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)) {
-                    this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
-                    fault_data=addr;
-                }
-                return res;
-            } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
-                fault_data=ta.addr;
-                return iss::Err;
-            }
-
-            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
-            if ((paddr.val + length) > mem.size()) return iss::Err;
-            switch (paddr.val) {
-            case 0x10013000: // UART0 base, TXFIFO reg
-            case 0x10023000: // UART1 base, TXFIFO reg
-                uart_buf << (char)data[0];
-                if (((char)data[0]) == '\n' || data[0] == 0) {
-                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-                    // '"<<uart_buf.str()<<"'";
-                    std::cout << uart_buf.str();
-                    uart_buf.str("");
-                }
-                return iss::Ok;
-            case 0x10008000: { // HFROSC base, hfrosccfg reg
-                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = paddr.val & mem.page_addr_mask;
-                std::copy(data, data + length, p.data() + offs);
-                auto &x = *(p.data() + offs + 3);
-                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-                return iss::Ok;
-            }
-            case 0x10008008: { // HFROSC base, pllcfg reg
-                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = paddr.val & mem.page_addr_mask;
-                std::copy(data, data + length, p.data() + offs);
-                auto &x = *(p.data() + offs + 3);
-                x |= 0x80; // set pll lock upon writing
-                return iss::Ok;
-            } break;
-            default: {}
-            }
-        } break;
-        case traits<BASE>::CSR: {
-            if (length != sizeof(reg_t)) return iss::Err;
-            return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
-        } break;
-        case traits<BASE>::FENCE: {
-            if ((addr + length) > mem.size()) return iss::Err;
-            switch (addr) {
-            case 2:
-            case 3: {
-                ptw.clear();
-                auto tvm = state.mstatus.TVM;
-                return iss::Ok;
-            }
-            }
-        } break;
-        case traits<BASE>::RES: {
-            atomic_reservation[addr] = data[0];
-        } break;
-        default:
-            return iss::Err;
-        }
-        return iss::Ok;
-    } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
-        fault_data=ta.addr;
-        return iss::Err;
-    }
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
-    if (addr >= csr.size()) return iss::Err;
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
-        throw illegal_instruction_fault(this->fault_data);
-    auto it = csr_rd_cb.find(addr);
-    if (it == csr_rd_cb.end() || !it->second) // non existent register
-        throw illegal_instruction_fault(this->fault_data);
-    return (this->*(it->second))(addr, val);
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
-    if (addr >= csr.size()) return iss::Err;
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
-        throw illegal_instruction_fault(this->fault_data);
-    if((addr&0xc00)==0xc00) // writing to read-only region
-        throw illegal_instruction_fault(this->fault_data);
-    auto it = csr_wr_cb.find(addr);
-    if (it == csr_wr_cb.end() || !it->second) // non existent register
-        throw illegal_instruction_fault(this->fault_data);
-    return (this->*(it->second))(addr, val);
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
-    val = csr[addr];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_null(unsigned addr, reg_t &val) {
-    val = 0;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
-    csr[addr] = val;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
-    if (addr == mcycle) {
-        val = static_cast<reg_t>(cycle_val);
-    } else if (addr == mcycleh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(cycle_val >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
-    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == mcycleh)
-            return iss::Err;
-        mcycle_csr = static_cast<uint64_t>(val);
-    } else {
-        if (addr == mcycle) {
-            mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
-        } else  {
-            mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
-        }
-    }
-    cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
-    if ((addr&0xff) == (minstret&0xff)) {
-        val = static_cast<reg_t>(this->reg.instret);
-    } else if ((addr&0xff) == (minstreth&0xff)) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(this->reg.instret >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
-    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if ((addr&0xff) == (minstreth&0xff))
-            return iss::Err;
-        this->reg.instret = static_cast<uint64_t>(val);
-    } else {
-        if ((addr&0xff) == (minstret&0xff)) {
-            this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
-        } else  {
-            this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
-        }
-    }
-    this->reg.instret--;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
-    if (addr == time) {
-        val = static_cast<reg_t>(time_val);
-    } else if (addr == timeh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(time_val >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
-    val = csr[mtvec] & ~2;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
-    val = state.mstatus & hart_state_type::get_mask();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
-    state.write_mstatus(val);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cause(unsigned addr, reg_t val) {
-    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
-    val = csr[mie];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
-    val = mhartid_reg;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
-    auto mask = get_irq_mask();
-    csr[mie] = (csr[mie] & ~mask) | (val & mask);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
-    val = csr[mip];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
-    auto mask = get_irq_mask();
-    mask &= ~(1 << 7); // MTIP is read only
-    csr[mip] = (csr[mip] & ~mask) | (val & mask);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) {
-    csr[addr] = val & get_pc_mask();
-    return iss::Ok;
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
-    switch (paddr.val) {
-    case 0x0200BFF8: { // CLINT base, mtime reg
-        if (sizeof(reg_t) < length) return iss::Err;
-        reg_t time_val;
-        this->read_csr(time, time_val);
-        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
-    } break;
-    case 0x10008000: {
-        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        uint64_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->reg.icount > 30000) data[3] |= 0x80;
-    } break;
-    default: {
-        for(auto offs=0U; offs<length; ++offs) {
-            *(data + offs)=mem[(paddr.val+offs)%mem.size()];
-        }
-    }
-    }
-    return iss::Ok;
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
-    switch (paddr.val) {
-    case 0x10013000: // UART0 base, TXFIFO reg
-    case 0x10023000: // UART1 base, TXFIFO reg
-        uart_buf << (char)data[0];
-        if (((char)data[0]) == '\n' || data[0] == 0) {
-            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-            // '"<<uart_buf.str()<<"'";
-            std::cout << uart_buf.str();
-            uart_buf.str("");
-        }
-        break;
-    case 0x10008000: { // HFROSC base, hfrosccfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-    } break;
-    case 0x10008008: { // HFROSC base, pllcfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        x |= 0x80; // set pll lock upon writing
-    } break;
-    default: {
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
-        // tohost handling in case of riscv-test
-        if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
-                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            auto tohost_lower =
-                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            if (tohost_lower || tohost_upper) {
-                uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
-                if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
-                    switch (hostvar >> 48) {
-                    case 0:
-                        if (hostvar != 0x1) {
-                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
-                        } else {
-                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
-                        }
-                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
-                        this->interrupt_sim=hostvar;
-                        break;
-                        //throw(iss::simulation_stopped(hostvar));
-                    case 0x0101: {
-                        char c = static_cast<char>(hostvar & 0xff);
-                        if (c == '\n' || c == 0) {
-                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
-                            uart_buf.str("");
-                        } else
-                            uart_buf << c;
-                        to_host_wr_cnt = 0;
-                    } break;
-                    default:
-                        break;
-                    }
-                } else if (tohost_lower)
-                    to_host_wr_cnt++;
-            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
-                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
-                uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
-                *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
-            }
-        }
-    }
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
-    BASE::reset(address);
-    state.mstatus = hart_state_type::mstatus_reset_val;
-}
-
-template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
-    //auto ideleg = csr[mideleg];
-    // Multiple simultaneous interrupts and traps at the same privilege level are
-    // handled in the following decreasing priority order:
-    // external interrupts, software interrupts, timer interrupts, then finally
-    // any synchronous traps.
-    auto ena_irq = csr[mip] & csr[mie];
-
-    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
-    auto enabled_interrupts = m_enabled ? ena_irq : 0;
-
-    if (enabled_interrupts != 0) {
-        int res = 0;
-        while ((enabled_interrupts & 1) == 0) {
-        	enabled_interrupts >>= 1;
-        	res++;
-        }
-        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
-    }
-}
-
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
-    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
-    // calculate and write mcause val
-    auto trap_id = bit_sub<0, 16>(flags);
-    auto cause = bit_sub<16, 15>(flags);
-    if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
-    // calculate effective privilege level
-    if (trap_id == 0) { // exception
-        // store ret addr in xepc register
-        csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
-        csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
-        fault_data = 0;
-    } else {
-        csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
-        this->reg.pending_trap = 0;
-    }
-    csr[mcause] = (trap_id << 31) + cause;
-    // update mstatus
-    // xPP field of mstatus is written with the active privilege mode at the time
-    // of the trap; the x PIE field of mstatus
-    // is written with the value of the active interrupt-enable bit at the time of
-    // the trap; and the x IE field of mstatus
-    // is cleared
-    // store the actual privilege level in yPP and store interrupt enable flags
-    state.mstatus.MPP = PRIV_M;
-    state.mstatus.MPIE = state.mstatus.MIE;
-    state.mstatus.MIE = false;
-
-    // get trap vector
-    auto ivec = csr[mtvec];
-    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
-    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x3UL;
-    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-    // reset trap state
-    this->reg.PRIV = PRIV_M;
-    this->reg.trap_state = 0;
-    std::array<char, 32> buffer;
-#if defined(_MSC_VER)
-    sprintf(buffer.data(), "0x%016llx", addr);
-#else
-    sprintf(buffer.data(), "0x%016lx", addr);
-#endif
-    if((flags&0xffffffff) != 0xffffffff)
-    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
-                       << " at address " << buffer.data() << " occurred";
-    return this->reg.NEXT_PC;
-}
-
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
-    state.mstatus.MIE = state.mstatus.MPIE;
-    state.mstatus.MPIE = 1;
-    // sets the pc to the value stored in the x epc register.
-    this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
-    CLOG(INFO, disass) << "Executing xRET";
-    check_interrupt();
-    return this->reg.NEXT_PC;
-}
-
-} // namespace arch
-} // namespace iss
-
-#endif /* _RISCV_HART_M_P_H */

incl/iss/arch/tgc_c.h

@@ -1,282 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#ifndef _TGC_C_H_
-#define _TGC_C_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct tgc_c;
-
-template <> struct traits<tgc_c> {
-
-    constexpr static char const* const core_type = "TGC_C";
-    
-    static constexpr std::array<const char*, 35> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
- 
-    static constexpr std::array<const char*, 35> reg_aliases{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
-
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
-        TRAP_STATE=NUM_REGS,
-        PENDING_TRAP,
-        ICOUNT,
-        CYCLE,
-        INSTRET
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
-    static constexpr std::array<const uint32_t, 40> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64,64,64}};
-
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,153,161}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, CSR, FENCE, RES };
-    
-    enum class opcode_e : unsigned short {
-        LUI = 0,
-        AUIPC = 1,
-        JAL = 2,
-        JALR = 3,
-        BEQ = 4,
-        BNE = 5,
-        BLT = 6,
-        BGE = 7,
-        BLTU = 8,
-        BGEU = 9,
-        LB = 10,
-        LH = 11,
-        LW = 12,
-        LBU = 13,
-        LHU = 14,
-        SB = 15,
-        SH = 16,
-        SW = 17,
-        ADDI = 18,
-        SLTI = 19,
-        SLTIU = 20,
-        XORI = 21,
-        ORI = 22,
-        ANDI = 23,
-        SLLI = 24,
-        SRLI = 25,
-        SRAI = 26,
-        ADD = 27,
-        SUB = 28,
-        SLL = 29,
-        SLT = 30,
-        SLTU = 31,
-        XOR = 32,
-        SRL = 33,
-        SRA = 34,
-        OR = 35,
-        AND = 36,
-        FENCE = 37,
-        ECALL = 38,
-        EBREAK = 39,
-        URET = 40,
-        SRET = 41,
-        MRET = 42,
-        WFI = 43,
-        CSRRW = 44,
-        CSRRS = 45,
-        CSRRC = 46,
-        CSRRWI = 47,
-        CSRRSI = 48,
-        CSRRCI = 49,
-        MUL = 50,
-        MULH = 51,
-        MULHSU = 52,
-        MULHU = 53,
-        DIV = 54,
-        DIVU = 55,
-        REM = 56,
-        REMU = 57,
-        CADDI4SPN = 58,
-        CLW = 59,
-        CSW = 60,
-        CADDI = 61,
-        CNOP = 62,
-        CJAL = 63,
-        CLI = 64,
-        CLUI = 65,
-        CADDI16SP = 66,
-        __reserved_clui = 67,
-        CSRLI = 68,
-        CSRAI = 69,
-        CANDI = 70,
-        CSUB = 71,
-        CXOR = 72,
-        COR = 73,
-        CAND = 74,
-        CJ = 75,
-        CBEQZ = 76,
-        CBNEZ = 77,
-        CSLLI = 78,
-        CLWSP = 79,
-        CMV = 80,
-        CJR = 81,
-        __reserved_cmv = 82,
-        CADD = 83,
-        CJALR = 84,
-        CEBREAK = 85,
-        CSWSP = 86,
-        DII = 87,
-        MAX_OPCODE
-    };
-};
-
-struct tgc_c: public arch_if {
-
-    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
-    using reg_t =  typename traits<tgc_c>::reg_t;
-    using addr_t = typename traits<tgc_c>::addr_t;
-
-    tgc_c();
-    ~tgc_c();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-#pragma pack(push, 1)
-    struct TGC_C_regs { 
-        uint32_t X0 = 0; 
-        uint32_t X1 = 0; 
-        uint32_t X2 = 0; 
-        uint32_t X3 = 0; 
-        uint32_t X4 = 0; 
-        uint32_t X5 = 0; 
-        uint32_t X6 = 0; 
-        uint32_t X7 = 0; 
-        uint32_t X8 = 0; 
-        uint32_t X9 = 0; 
-        uint32_t X10 = 0; 
-        uint32_t X11 = 0; 
-        uint32_t X12 = 0; 
-        uint32_t X13 = 0; 
-        uint32_t X14 = 0; 
-        uint32_t X15 = 0; 
-        uint32_t X16 = 0; 
-        uint32_t X17 = 0; 
-        uint32_t X18 = 0; 
-        uint32_t X19 = 0; 
-        uint32_t X20 = 0; 
-        uint32_t X21 = 0; 
-        uint32_t X22 = 0; 
-        uint32_t X23 = 0; 
-        uint32_t X24 = 0; 
-        uint32_t X25 = 0; 
-        uint32_t X26 = 0; 
-        uint32_t X27 = 0; 
-        uint32_t X28 = 0; 
-        uint32_t X29 = 0; 
-        uint32_t X30 = 0; 
-        uint32_t X31 = 0; 
-        uint32_t PC = 0; 
-        uint32_t NEXT_PC = 0; 
-        uint8_t PRIV = 0;
-        uint32_t trap_state = 0, pending_trap = 0;
-        uint64_t icount = 0;
-        uint64_t cycle = 0;
-        uint64_t instret = 0;
-        uint32_t last_branch;
-    } reg;
-#pragma pack(pop)
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-    uint32_t get_fcsr(){return 0;}
-    void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _TGC_C_H_ */

softfloat/.gitignore

@@ -0,0 +1,2 @@
+build/*/*.o
+build/*/*.a

softfloat/CMakeLists.txt

@@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
 # Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
 set(VERSION "3e")
 
-include(Common)
+#include(Common)
 include(GNUInstallDirs)
 
 set(SPECIALIZATION RISCV)
@@ -327,7 +327,7 @@ set(OTHERS
 
 set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS})
 
-add_library(softfloat ${LIB_SOURCES})
+add_library(softfloat STATIC ${LIB_SOURCES})
 set_property(TARGET softfloat PROPERTY C_STANDARD 99)
 target_compile_definitions(softfloat PRIVATE 
 	SOFTFLOAT_ROUND_ODD 
@@ -347,7 +347,7 @@ set_target_properties(softfloat PROPERTIES
 
 install(TARGETS softfloat
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs   # static lib
   LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
   FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel   # headers for mac (note the different component -> different package)

softfloat/README.md

@@ -0,0 +1,24 @@
+
+Package Overview for Berkeley SoftFloat Release 3e
+==================================================
+
+John R. Hauser<br>
+2018 January 20
+
+
+Berkeley SoftFloat is a software implementation of binary floating-point
+that conforms to the IEEE Standard for Floating-Point Arithmetic.  SoftFloat
+is distributed in the form of C source code.  Building the SoftFloat sources
+generates a library file (typically `softfloat.a` or `libsoftfloat.a`)
+containing the floating-point subroutines.
+
+
+The SoftFloat package is documented in the following files in the `doc`
+subdirectory:
+
+* [SoftFloat.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat.html) Documentation for using the SoftFloat functions.
+* [SoftFloat-source.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-source.html) Documentation for building SoftFloat.
+* [SoftFloat-history.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-history.html) History of the major changes to SoftFloat.
+
+Other files in the package comprise the source code for SoftFloat.
+

softfloat/build/Linux-RISCV64-GCC/Makefile

@@ -0,0 +1,399 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= RISCV
+MARCH ?= rv64gcv_zfh_zfhmin
+MABI ?= lp64d
+
+SOFTFLOAT_OPTS ?= \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_FAST_DIV64TO32
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  riscv64-unknown-linux-gnu-gcc -c -march=$(MARCH) -mabi=$(MABI) -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
+    $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+MAKELIB = ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_eq128$(OBJ) \
+  s_le128$(OBJ) \
+  s_lt128$(OBJ) \
+  s_shortShiftLeft128$(OBJ) \
+  s_shortShiftRight128$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64Extra$(OBJ) \
+  s_shortShiftRightJam128$(OBJ) \
+  s_shortShiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64Extra$(OBJ) \
+  s_shiftRightJam128$(OBJ) \
+  s_shiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam256M$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_add128$(OBJ) \
+  s_add256M$(OBJ) \
+  s_sub128$(OBJ) \
+  s_sub256M$(OBJ) \
+  s_mul64ByShifted32To128$(OBJ) \
+  s_mul64To128$(OBJ) \
+  s_mul128By32$(OBJ) \
+  s_mul128To256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_bf16UIToCommonNaN$(OBJ) \
+  s_commonNaNToBF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80UIToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80UI$(OBJ) \
+  s_propagateNaNExtF80UI$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128UIToCommonNaN$(OBJ) \
+  s_commonNaNToF128UI$(OBJ) \
+  s_propagateNaNF128UI$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundToI64$(OBJ) \
+  s_normSubnormalBF16Sig$(OBJ) \
+  s_roundPackToBF16$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_normSubnormalExtF80Sig$(OBJ) \
+  s_roundPackToExtF80$(OBJ) \
+  s_normRoundPackToExtF80$(OBJ) \
+  s_addMagsExtF80$(OBJ) \
+  s_subMagsExtF80$(OBJ) \
+  s_normSubnormalF128Sig$(OBJ) \
+  s_roundPackToF128$(OBJ) \
+  s_normRoundPackToF128$(OBJ) \
+  s_addMagsF128$(OBJ) \
+  s_subMagsF128$(OBJ) \
+  s_mulAddF128$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  bf16_isSignalingNaN$(OBJ) \
+  bf16_to_f32$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_bf16$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80_to_ui32$(OBJ) \
+  extF80_to_ui64$(OBJ) \
+  extF80_to_i32$(OBJ) \
+  extF80_to_i64$(OBJ) \
+  extF80_to_ui32_r_minMag$(OBJ) \
+  extF80_to_ui64_r_minMag$(OBJ) \
+  extF80_to_i32_r_minMag$(OBJ) \
+  extF80_to_i64_r_minMag$(OBJ) \
+  extF80_to_f16$(OBJ) \
+  extF80_to_f32$(OBJ) \
+  extF80_to_f64$(OBJ) \
+  extF80_to_f128$(OBJ) \
+  extF80_roundToInt$(OBJ) \
+  extF80_add$(OBJ) \
+  extF80_sub$(OBJ) \
+  extF80_mul$(OBJ) \
+  extF80_div$(OBJ) \
+  extF80_rem$(OBJ) \
+  extF80_sqrt$(OBJ) \
+  extF80_eq$(OBJ) \
+  extF80_le$(OBJ) \
+  extF80_lt$(OBJ) \
+  extF80_eq_signaling$(OBJ) \
+  extF80_le_quiet$(OBJ) \
+  extF80_lt_quiet$(OBJ) \
+  extF80_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128_to_ui32$(OBJ) \
+  f128_to_ui64$(OBJ) \
+  f128_to_i32$(OBJ) \
+  f128_to_i64$(OBJ) \
+  f128_to_ui32_r_minMag$(OBJ) \
+  f128_to_ui64_r_minMag$(OBJ) \
+  f128_to_i32_r_minMag$(OBJ) \
+  f128_to_i64_r_minMag$(OBJ) \
+  f128_to_f16$(OBJ) \
+  f128_to_f32$(OBJ) \
+  f128_to_extF80$(OBJ) \
+  f128_to_f64$(OBJ) \
+  f128_roundToInt$(OBJ) \
+  f128_add$(OBJ) \
+  f128_sub$(OBJ) \
+  f128_mul$(OBJ) \
+  f128_mulAdd$(OBJ) \
+  f128_div$(OBJ) \
+  f128_rem$(OBJ) \
+  f128_sqrt$(OBJ) \
+  f128_eq$(OBJ) \
+  f128_le$(OBJ) \
+  f128_lt$(OBJ) \
+  f128_eq_signaling$(OBJ) \
+  f128_le_quiet$(OBJ) \
+  f128_lt_quiet$(OBJ) \
+  f128_isSignalingNaN$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+

softfloat/build/Linux-RISCV64-GCC/platform.h

@@ -0,0 +1,54 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_INTRINSIC_INT128 1
+#include "opts-GCC.h"
+

softfloat/build/Linux-x86_64-GCC/Makefile

@@ -94,6 +94,8 @@ OBJS_SPECIALIZE = \
   s_f16UIToCommonNaN$(OBJ) \
   s_commonNaNToF16UI$(OBJ) \
   s_propagateNaNF16UI$(OBJ) \
+  s_bf16UIToCommonNaN$(OBJ) \
+  s_commonNaNToBF16UI$(OBJ) \
   s_f32UIToCommonNaN$(OBJ) \
   s_commonNaNToF32UI$(OBJ) \
   s_propagateNaNF32UI$(OBJ) \
@@ -114,6 +116,8 @@ OBJS_OTHERS = \
   s_roundToUI64$(OBJ) \
   s_roundToI32$(OBJ) \
   s_roundToI64$(OBJ) \
+  s_normSubnormalBF16Sig$(OBJ) \
+  s_roundPackToBF16$(OBJ) \
   s_normSubnormalF16Sig$(OBJ) \
   s_roundPackToF16$(OBJ) \
   s_normRoundPackToF16$(OBJ) \
@@ -172,6 +176,8 @@ OBJS_OTHERS = \
   i64_to_extF80M$(OBJ) \
   i64_to_f128$(OBJ) \
   i64_to_f128M$(OBJ) \
+  bf16_isSignalingNaN$(OBJ) \
+  bf16_to_f32$(OBJ) \
   f16_to_ui32$(OBJ) \
   f16_to_ui64$(OBJ) \
   f16_to_i32$(OBJ) \
@@ -209,6 +215,7 @@ OBJS_OTHERS = \
   f32_to_ui64_r_minMag$(OBJ) \
   f32_to_i32_r_minMag$(OBJ) \
   f32_to_i64_r_minMag$(OBJ) \
+  f32_to_bf16$(OBJ) \
   f32_to_f16$(OBJ) \
   f32_to_f64$(OBJ) \
   f32_to_extF80$(OBJ) \

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -54,4 +54,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #endif
 #include "opts-GCC.h"
-

softfloat/build/template-FAST_INT64/Makefile

@@ -115,6 +115,8 @@ OBJS_OTHERS = \
   s_roundToUI64$(OBJ) \
   s_roundToI32$(OBJ) \
   s_roundToI64$(OBJ) \
+  s_normSubnormalBF16Sig$(OBJ) \
+  s_roundPackToBF16$(OBJ) \
   s_normSubnormalF16Sig$(OBJ) \
   s_roundPackToF16$(OBJ) \
   s_normRoundPackToF16$(OBJ) \
@@ -173,6 +175,8 @@ OBJS_OTHERS = \
   i64_to_extF80M$(OBJ) \
   i64_to_f128$(OBJ) \
   i64_to_f128M$(OBJ) \
+  bf16_isSignalingNaN$(OBJ) \
+  bf16_to_f32$(OBJ) \
   f16_to_ui32$(OBJ) \
   f16_to_ui64$(OBJ) \
   f16_to_i32$(OBJ) \
@@ -210,6 +214,7 @@ OBJS_OTHERS = \
   f32_to_ui64_r_minMag$(OBJ) \
   f32_to_i32_r_minMag$(OBJ) \
   f32_to_i64_r_minMag$(OBJ) \
+  f32_to_bf16$(OBJ) \
   f32_to_f16$(OBJ) \
   f32_to_f64$(OBJ) \
   f32_to_extF80$(OBJ) \

softfloat/doc/SoftFloat.html

@@ -508,7 +508,7 @@ significant extra cost.
 On computers where the word size is <NOBR>64 bits</NOBR> or larger, both
 function versions (<CODE>f128M_add</CODE> and <CODE>f128_add</CODE>) are
 provided, because the cost of passing by value is then more reasonable.
-Applications that must be portable accross both classes of computers must use
+Applications that must be portable across both classes of computers must use
 the pointer-based functions, as these are always implemented.
 However, if it is known that SoftFloat includes the by-value functions for all
 platforms of interest, programmers can use whichever version they prefer.

softfloat/source/8086-SSE/s_bf16UIToCommonNaN.c

@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming `uiA' has the bit pattern of a BF16 NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_bf16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNBF16UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>15;
+    zPtr->v64  = (uint_fast64_t) uiA<<56;
+    zPtr->v0   = 0;
+
+}
+

softfloat/source/8086-SSE/s_commonNaNToBF16UI.c

@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a BF16 NaN, and 
+| returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToBF16UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast16_t) aPtr->sign<<15 | 0x7FC0 | aPtr->v64>>56;
+
+}
+

softfloat/source/8086-SSE/specialize.h

@@ -117,6 +117,27 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 uint_fast16_t
  softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
+/*----------------------------------------------------------------------------
+| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
+| 16-bit brain floating-point (BF16) signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNBF16UI( uiA ) ((((uiA) & 0x7FC0) == 0x7F80) && ((uiA) & 0x003F))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 16-bit BF16 floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_bf16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToBF16UI( const struct commonNaN *aPtr );
+
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
 *----------------------------------------------------------------------------*/

softfloat/source/RISCV/s_bf16UIToCommonNaN.c

@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+

softfloat/source/RISCV/s_commonNaNToBF16UI.c

@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+

softfloat/source/RISCV/s_commonNaNToExtF80M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,9 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdint.h>
 #include "platform.h"
-#include "internals.h"
+#include "softfloat_types.h"
+
+#define softfloat_commonNaNToExtF80M softfloat_commonNaNToExtF80M
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -49,8 +50,8 @@ void
      const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
 {
 
-    zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
-    zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signif  = defaultNaNExtF80UI0;
 
 }
 

softfloat/source/RISCV/s_commonNaNToExtF80UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,9 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdint.h>
 #include "platform.h"
-#include "primitives.h"
+#include "primitiveTypes.h"
+
+#define softfloat_commonNaNToExtF80UI softfloat_commonNaNToExtF80UI
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -48,8 +49,8 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
 {
     struct uint128 uiZ;
 
-    uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
-    uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+    uiZ.v64 = defaultNaNExtF80UI64;
+    uiZ.v0  = defaultNaNExtF80UI0;
     return uiZ;
 
 }

softfloat/source/RISCV/s_commonNaNToF128M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -36,7 +36,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #include <stdint.h>
 #include "platform.h"
-#include "primitives.h"
+#include "primitiveTypes.h"
+
+#define softfloat_commonNaNToF128M softfloat_commonNaNToF128M
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -49,8 +51,10 @@ void
  softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
 {
 
-    softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
-    zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
+    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
 
 }
 

softfloat/source/RISCV/s_commonNaNToF128UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,9 +34,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdint.h>
 #include "platform.h"
-#include "primitives.h"
+#include "primitiveTypes.h"
+
+#define softfloat_commonNaNToF128UI softfloat_commonNaNToF128UI
 #include "specialize.h"
 
 /*----------------------------------------------------------------------------
@@ -47,8 +48,8 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
 {
     struct uint128 uiZ;
 
-    uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
-    uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
     return uiZ;
 
 }

softfloat/source/RISCV/s_commonNaNToF16UI.c

@@ -1,51 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
-California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
 /*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr )
-{
-
-    return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54;
-
-}
 

softfloat/source/RISCV/s_commonNaNToF32UI.c

@@ -1,51 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
 /*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
-{
-
-    return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41;
-
-}
 

softfloat/source/RISCV/s_commonNaNToF64UI.c

@@ -1,53 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
 /*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
-{
-
-    return
-        (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 )
-            | aPtr->v64>>12;
-
-}
 

softfloat/source/RISCV/s_extF80MToCommonNaN.c

@@ -1,62 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
 /*----------------------------------------------------------------------------
-| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is
-| a NaN, converts this NaN to the common NaN form, and stores the resulting
-| common NaN at the location pointed to by `zPtr'.  If the NaN is a signaling
-| NaN, the invalid exception is raised.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr )
-{
-
-    if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = signExtF80UI64( aSPtr->signExp );
-    zPtr->v64 = aSPtr->signif<<1;
-    zPtr->v0  = 0;
-
-}
 

softfloat/source/RISCV/s_extF80UIToCommonNaN.c

@@ -1,62 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-#include "softfloat.h"
-
 /*----------------------------------------------------------------------------
-| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
-| has the bit pattern of an 80-bit extended floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
-{
-
-    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = uiA64>>15;
-    zPtr->v64  = uiA0<<1;
-    zPtr->v0   = 0;
-
-}
 

softfloat/source/RISCV/s_f128MToCommonNaN.c

@@ -1,62 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "specialize.h"
-#include "softfloat.h"
-
 /*----------------------------------------------------------------------------
-| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN,
-| converts this NaN to the common NaN form, and stores the resulting common
-| NaN at the location pointed to by `zPtr'.  If the NaN is a signaling NaN,
-| the invalid exception is raised.  Argument `aWPtr' points to an array of
-| four 32-bit elements that concatenate in the platform's normal endian order
-| to form a 128-bit floating-point value.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr )
-{
-
-    if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = aWPtr[indexWordHi( 4 )]>>31;
-    softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 );
-
-}
 

softfloat/source/RISCV/s_f128UIToCommonNaN.c

@@ -1,65 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "specialize.h"
-#include "softfloat.h"
-
 /*----------------------------------------------------------------------------
-| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
-| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
-| the common NaN form, and stores the resulting common NaN at the location
-| pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid exception
-| is raised.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
-{
-    struct uint128 NaNSig;
-
-    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
-    zPtr->sign = uiA64>>63;
-    zPtr->v64  = NaNSig.v64;
-    zPtr->v0   = NaNSig.v0;
-
-}
 

softfloat/source/RISCV/s_f16UIToCommonNaN.c

@@ -1,59 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
-California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-#include "softfloat.h"
-
 /*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
-{
-
-    if ( softfloat_isSigNaNF16UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = uiA>>15;
-    zPtr->v64  = (uint_fast64_t) uiA<<54;
-    zPtr->v0   = 0;
-
-}
 

softfloat/source/RISCV/s_f32UIToCommonNaN.c

@@ -1,59 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-#include "softfloat.h"
-
 /*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
-{
-
-    if ( softfloat_isSigNaNF32UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = uiA>>31;
-    zPtr->v64  = (uint_fast64_t) uiA<<41;
-    zPtr->v0   = 0;
-
-}
 

softfloat/source/RISCV/s_f64UIToCommonNaN.c

@@ -1,59 +1,5 @@
 
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-#include "softfloat.h"
-
 /*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| This file intentionally contains no code.
 *----------------------------------------------------------------------------*/
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
-{
-
-    if ( softfloat_isSigNaNF64UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = uiA>>63;
-    zPtr->v64  = uiA<<12;
-    zPtr->v0   = 0;
-
-}
 

softfloat/source/RISCV/s_propagateNaNExtF80M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,10 +34,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "internals.h"
+#include "primitiveTypes.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -54,54 +53,22 @@ void
      struct extFloat80M *zSPtr
  )
 {
-    bool isSigNaNA;
-    const struct extFloat80M *sPtr;
-    bool isSigNaNB;
-    uint_fast16_t uiB64;
-    uint64_t uiB0;
-    uint_fast16_t uiA64;
-    uint64_t uiA0;
-    uint_fast16_t uiMagA64, uiMagB64;
+    uint_fast16_t ui64;
+    uint_fast64_t ui0;
 
-    isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr );
-    sPtr = aSPtr;
-    if ( ! bSPtr ) {
-        if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid );
-        goto copy;
-    }
-    isSigNaNB = extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr );
-    if ( isSigNaNA | isSigNaNB ) {
+    ui64 = aSPtr->signExp;
+    ui0  = aSPtr->signif;
+    if (
+        softfloat_isSigNaNExtF80UI( ui64, ui0 )
+            || (bSPtr
+                    && (ui64 = bSPtr->signExp,
+                        ui0  = bSPtr->signif,
+                        softfloat_isSigNaNExtF80UI( ui64, ui0 )))
+    ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
-        if ( isSigNaNA ) {
-            uiB64 = bSPtr->signExp;
-            if ( isSigNaNB ) goto returnLargerUIMag;
-            uiB0 = bSPtr->signif;
-            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto copyB;
-            goto copy;
-        } else {
-            uiA64 = aSPtr->signExp;
-            uiA0 = aSPtr->signif;
-            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto copy;
-            goto copyB;
     }
-    }
-    uiB64 = bSPtr->signExp;
- returnLargerUIMag:
-    uiA64 = aSPtr->signExp;
-    uiMagA64 = uiA64 & 0x7FFF;
-    uiMagB64 = uiB64 & 0x7FFF;
-    if ( uiMagA64 < uiMagB64 ) goto copyB;
-    if ( uiMagB64 < uiMagA64 ) goto copy;
-    uiA0 = aSPtr->signif;
-    uiB0 = bSPtr->signif;
-    if ( uiA0 < uiB0 ) goto copyB;
-    if ( uiB0 < uiA0 ) goto copy;
-    if ( uiA64 < uiB64 ) goto copy;
- copyB:
-    sPtr = bSPtr;
- copy:
-    zSPtr->signExp = sPtr->signExp;
-    zSPtr->signif = sPtr->signif | UINT64_C( 0xC000000000000000 );
+    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signif  = defaultNaNExtF80UI0;
 
 }
 

softfloat/source/RISCV/s_propagateNaNExtF80UI.c

@@ -4,7 +4,7 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
 California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -34,17 +34,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "internals.h"
+#include "primitiveTypes.h"
 #include "specialize.h"
 #include "softfloat.h"
 
 /*----------------------------------------------------------------------------
-| Interpreting the unsigned integer formed from concatenating 'uiA64' and
-| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
-| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| Interpreting the unsigned integer formed from concatenating `uiA64' and
+| `uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating `uiB64' and `uiB0' as another
 | 80-bit extended floating-point value, and assuming at least on of these
 | floating-point values is a NaN, returns the bit pattern of the combined NaN
 | result.  If either original floating-point value is a signaling NaN, the
@@ -58,48 +57,16 @@ struct uint128
      uint_fast64_t uiB0
  )
 {
-    bool isSigNaNA, isSigNaNB;
-    uint_fast64_t uiNonsigA0, uiNonsigB0;
-    uint_fast16_t uiMagA64, uiMagB64;
     struct uint128 uiZ;
 
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 );
-    isSigNaNB = softfloat_isSigNaNExtF80UI( uiB64, uiB0 );
-    /*------------------------------------------------------------------------
-    | Make NaNs non-signaling.
-    *------------------------------------------------------------------------*/
-    uiNonsigA0 = uiA0 | UINT64_C( 0xC000000000000000 );
-    uiNonsigB0 = uiB0 | UINT64_C( 0xC000000000000000 );
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    if ( isSigNaNA | isSigNaNB ) {
+    if (
+           softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+        || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+    ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
-        if ( isSigNaNA ) {
-            if ( isSigNaNB ) goto returnLargerMag;
-            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB;
-            goto returnA;
-        } else {
-            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto returnA;
-            goto returnB;
     }
-    }
- returnLargerMag:
-    uiMagA64 = uiA64 & 0x7FFF;
-    uiMagB64 = uiB64 & 0x7FFF;
-    if ( uiMagA64 < uiMagB64 ) goto returnB;
-    if ( uiMagB64 < uiMagA64 ) goto returnA;
-    if ( uiA0 < uiB0 ) goto returnB;
-    if ( uiB0 < uiA0 ) goto returnA;
-    if ( uiA64 < uiB64 ) goto returnA;
- returnB:
-    uiZ.v64 = uiB64;
-    uiZ.v0  = uiNonsigB0;
-    return uiZ;
- returnA:
-    uiZ.v64 = uiA64;
-    uiZ.v0  = uiNonsigA0;
+    uiZ.v64 = defaultNaNExtF80UI64;
+    uiZ.v0  = defaultNaNExtF80UI0;
     return uiZ;
 
 }

softfloat/source/RISCV/s_propagateNaNF128M.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015, 2018 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,43 +34,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "internals.h"
+#include "primitiveTypes.h"
 #include "specialize.h"
 #include "softfloat.h"
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
-| `aWPtr' and `bWPtr' is a NaN, stores the combined NaN result at the location
-| pointed to by `zWPtr'.  If either original floating-point value is a
-| signaling NaN, the invalid exception is raised.  Each of `aWPtr', `bWPtr',
-| and `zWPtr' points to an array of four 32-bit elements that concatenate in
+| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by 'zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
 void
  softfloat_propagateNaNF128M(
      const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr )
 {
-    bool isSigNaNA;
-    const uint32_t *ptr;
 
-    ptr = aWPtr;
-    isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr );
     if (
-        isSigNaNA
+        f128M_isSignalingNaN( (const float128_t *) aWPtr )
             || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr ))
     ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
-        if ( isSigNaNA ) goto copy;
     }
-    if ( ! softfloat_isNaNF128M( aWPtr ) ) ptr = bWPtr;
- copy:
-    zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000;
-    zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )];
-    zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )];
-    zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )];
+    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
 
 }
 

softfloat/source/RISCV/s_propagateNaNF128UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,10 +34,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "internals.h"
+#include "primitiveTypes.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -58,23 +57,16 @@ struct uint128
      uint_fast64_t uiB0
  )
 {
-    bool isSigNaNA;
     struct uint128 uiZ;
 
-    isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 );
-    if ( isSigNaNA || softfloat_isSigNaNF128UI( uiB64, uiB0 ) ) {
+    if (
+           softfloat_isSigNaNF128UI( uiA64, uiA0 )
+        || softfloat_isSigNaNF128UI( uiB64, uiB0 )
+    ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
-        if ( isSigNaNA ) goto returnNonsigA;
     }
-    if ( isNaNF128UI( uiA64, uiA0 ) ) {
- returnNonsigA:
-        uiZ.v64 = uiA64;
-        uiZ.v0  = uiA0;
-    } else {
-        uiZ.v64 = uiB64;
-        uiZ.v0  = uiB0;
-    }
-    uiZ.v64 |= UINT64_C( 0x0000800000000000 );
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
     return uiZ;
 
 }

softfloat/source/RISCV/s_propagateNaNF16UI.c

@@ -4,7 +4,7 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
 California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -34,10 +34,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -50,14 +48,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 uint_fast16_t
  softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB )
 {
-    bool isSigNaNA;
 
-    isSigNaNA = softfloat_isSigNaNF16UI( uiA );
-    if ( isSigNaNA || softfloat_isSigNaNF16UI( uiB ) ) {
+    if ( softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
-        if ( isSigNaNA ) return uiA | 0x0200;
     }
-    return (isNaNF16UI( uiA ) ? uiA : uiB) | 0x0200;
+    return defaultNaNF16UI;
 
 }
 

softfloat/source/RISCV/s_propagateNaNF32UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,10 +34,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -50,14 +48,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 uint_fast32_t
  softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )
 {
-    bool isSigNaNA;
 
-    isSigNaNA = softfloat_isSigNaNF32UI( uiA );
-    if ( isSigNaNA || softfloat_isSigNaNF32UI( uiB ) ) {
+    if ( softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
-        if ( isSigNaNA ) return uiA | 0x00400000;
     }
-    return (isNaNF32UI( uiA ) ? uiA : uiB) | 0x00400000;
+    return defaultNaNF32UI;
 
 }
 

softfloat/source/RISCV/s_propagateNaNF64UI.c

@@ -4,8 +4,8 @@
 This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
 Package, Release 3e, by John R. Hauser.
 
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -34,10 +34,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-#include <stdbool.h>
 #include <stdint.h>
 #include "platform.h"
-#include "internals.h"
 #include "specialize.h"
 #include "softfloat.h"
 
@@ -50,14 +48,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 uint_fast64_t
  softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
 {
-    bool isSigNaNA;
 
-    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
-    if ( isSigNaNA || softfloat_isSigNaNF64UI( uiB ) ) {
+    if ( softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) ) {
         softfloat_raiseFlags( softfloat_flag_invalid );
-        if ( isSigNaNA ) return uiA | UINT64_C( 0x0008000000000000 );
     }
-    return (isNaNF64UI( uiA ) ? uiA : uiB) | UINT64_C( 0x0008000000000000 );
+    return defaultNaNF64UI;
 
 }
 

softfloat/source/RISCV/specialize.h

@@ -51,19 +51,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | The values to return on conversions to 32-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
-#define ui32_fromPosOverflow UINT32_C(0xFFFFFFFF)
-#define ui32_fromNegOverflow UINT32_C(0x0)
-#define ui32_fromNaN         UINT32_C(0xFFFFFFFF)
-#define i32_fromPosOverflow   INT64_C(0x7FFFFFFF)
-#define i32_fromNegOverflow  (-INT64_C(0x7FFFFFFF)-1)
-#define i32_fromNaN           INT64_C(0x7FFFFFFF)
+#define ui32_fromPosOverflow 0xFFFFFFFF
+#define ui32_fromNegOverflow 0
+#define ui32_fromNaN         0xFFFFFFFF
+#define i32_fromPosOverflow  0x7FFFFFFF
+#define i32_fromNegOverflow  (-0x7FFFFFFF - 1)
+#define i32_fromNaN          0x7FFFFFFF
 
 /*----------------------------------------------------------------------------
 | The values to return on conversions to 64-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
 #define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
-#define ui64_fromNegOverflow UINT64_C( 0x0 )
+#define ui64_fromNegOverflow 0
 #define ui64_fromNaN         UINT64_C( 0xFFFFFFFFFFFFFFFF )
 #define i64_fromPosOverflow  INT64_C( 0x7FFFFFFFFFFFFFFF )
 #define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
@@ -73,19 +73,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | "Common NaN" structure, used to transfer NaN representations from one format
 | to another.
 *----------------------------------------------------------------------------*/
-struct commonNaN {
-    bool sign;
-#ifdef LITTLEENDIAN
-    uint64_t v0, v64;
-#else
-    uint64_t v64, v0;
-#endif
-};
+struct commonNaN { char _unused; };
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 16-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF16UI 0xFE00
+#define defaultNaNF16UI 0x7E00
 
 /*----------------------------------------------------------------------------
 | Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
@@ -94,19 +87,34 @@ struct commonNaN {
 *----------------------------------------------------------------------------*/
 #define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
 
+/*----------------------------------------------------------------------------
+| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
+| 16-bit brain floating-point (BF16) signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNBF16UI( uiA ) ((((uiA) & 0x7FC0) == 0x7F80) && ((uiA) & 0x003F))
+
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
 | this NaN to the common NaN form, and stores the resulting common NaN at the
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 16-bit BF16 floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+#define softfloat_bf16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0040) ) softfloat_raiseFlags( softfloat_flag_invalid )
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+#define softfloat_commonNaNToF16UI( aPtr ) ((uint_fast16_t) defaultNaNF16UI)
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
@@ -117,6 +125,17 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 uint_fast16_t
  softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 16-bit BF16 floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNBF16UI 0x7FC0
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+#define softfloat_commonNaNToBF16UI( aPtr ) ((uint_fast16_t) defaultNaNBF16UI)
+
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
@@ -135,13 +154,13 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) softfloat_raiseFlags( softfloat_flag_invalid )
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+#define softfloat_commonNaNToF32UI( aPtr ) ((uint_fast32_t) defaultNaNF32UI)
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
@@ -170,13 +189,13 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+#define softfloat_commonNaNToF64UI( aPtr ) ((uint_fast64_t) defaultNaNF64UI)
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
@@ -190,7 +209,7 @@ uint_fast64_t
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNExtF80UI64 0xFFFF
+#define defaultNaNExtF80UI64 0x7FFF
 #define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
 
 /*----------------------------------------------------------------------------
@@ -215,16 +234,25 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToExtF80UI
+INLINE
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+    uiZ.v64 = defaultNaNExtF80UI64;
+    uiZ.v0  = defaultNaNExtF80UI0;
+    return uiZ;
+}
+#else
 struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+#endif
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -246,7 +274,7 @@ struct uint128
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 )
+#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 )
 #define defaultNaNF128UI0  UINT64_C( 0 )
 
 /*----------------------------------------------------------------------------
@@ -264,15 +292,24 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToF128UI
+INLINE
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+    return uiZ;
+}
+#else
 struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+#endif
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -304,18 +341,27 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToExtF80M
+INLINE
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
+    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signif  = defaultNaNExtF80UI0;
+}
+#else
 void
  softfloat_commonNaNToExtF80M(
      const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+#endif
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -333,7 +379,7 @@ void
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI96 0xFFFF8000
+#define defaultNaNF128UI96 0x7FFF8000
 #define defaultNaNF128UI64 0
 #define defaultNaNF128UI32 0
 #define defaultNaNF128UI0  0
@@ -346,8 +392,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +400,20 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToF128M
+INLINE
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
+    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
+}
+#else
 void
  softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+#endif
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by

softfloat/source/bf16_isSignalingNaN.c

@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool bf16_isSignalingNaN( bfloat16_t a )
+{
+    union ui16_bf16 uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNBF16UI( uA.ui );
+
+}
+

softfloat/source/bf16_to_f32.c

@@ -0,0 +1,90 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t bf16_to_f32( bfloat16_t a )
+{
+    union ui16_bf16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast16_t frac;
+    struct commonNaN commonNaN;
+    uint_fast32_t uiZ;
+    struct exp8_sig16 normExpSig;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signBF16UI( uiA );
+    exp  = expBF16UI( uiA );
+    frac = fracBF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    // NaN or Inf
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            softfloat_bf16UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
+        } else {
+            uiZ = packToF32UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    // packToF32UI simply packs bitfields without any numerical change
+    // which means it can be used directly for any BF16 to f32 conversions which
+    // does not require bits manipulation
+    // (that is everything where the 16-bit are just padded right with 16 zeros, including
+    //  subnormal numbers)
+    uiZ = packToF32UI( sign, exp, ((uint_fast32_t) frac) <<16 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+
+

softfloat/source/f32_to_bf16.c

@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#include <inttypes.h>
+#include <stdio.h>
+
+bfloat16_t f32_to_bf16( float32_t a )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t frac;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ, frac16;
+    union ui16_bf16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    frac = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    // infinity or NaN cases
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            // NaN case
+            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToBF16UI( &commonNaN );
+        } else {
+            // infinity case
+            uiZ = packToBF16UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    // frac is a 24-bit mantissa, right shifted by 9
+    // In the normal case, (24-9) = 15 are set 
+    frac16 = frac>>9 | ((frac & 0x1FF) != 0);
+    if ( ! (exp | frac16) ) {
+        uiZ = packToBF16UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    // softfloat_roundPackToBF16 exponent argument (2nd argument)
+    // must correspond to the exponent of fracIn[13] bits
+    // (fracIn is the 3rd and last argument) 
+    uint_fast32_t mask = exp ? 0x4000 : 0x0; // implicit one mask added if input is a normal number
+    // exponent for the lowest normal and largest subnormal should be equal
+    // but is not in IEEE encoding so mantissa must be partially normalized
+    // (by one bit) for subnormal numbers. Such that (exp - 1) corresponds
+    // to the exponent of frac16[13]
+    frac16 = frac16 << (exp ? 0 : 1);
+    return softfloat_roundPackToBF16( sign, exp - 1, frac16 | mask );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

softfloat/source/f32_to_f16.c

@@ -72,6 +72,9 @@ float16_t f32_to_f16( float32_t a )
     }
     /*------------------------------------------------------------------------
     *------------------------------------------------------------------------*/
+    // frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red
+    // into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice
+    // is OR-red with the sticky 
     frac16 = frac>>9 | ((frac & 0x1FF) != 0);
     if ( ! (exp | frac16) ) {
         uiZ = packToF16UI( sign, 0, 0 );

softfloat/source/include/internals.h

@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat_types.h"
 
 union ui16_f16 { uint16_t ui; float16_t f; };
+union ui16_bf16 { uint16_t ui; bfloat16_t f; };
 union ui32_f32 { uint32_t ui; float32_t f; };
 union ui64_f64 { uint64_t ui; float64_t f; };
 
@@ -99,6 +100,18 @@ float16_t
  softfloat_mulAddF16(
      uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t );
 
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define signBF16UI( a ) ((bool) ((uint16_t) (a)>>15))
+#define expBF16UI( a ) ((int_fast16_t) ((a)>>7) & 0xFF)
+#define fracBF16UI( a ) ((a) & 0x07F)
+#define packToBF16UI( sign, exp, sig ) (((uint16_t) (sign)<<15) + ((uint16_t) (exp)<<7) + (sig))
+
+#define isNaNBF16UI( a ) (((~(a) & 0x7FC0) == 0) && ((a) & 0x07F))
+
+bfloat16_t softfloat_roundPackToBF16( bool, int_fast16_t, uint_fast16_t );
+struct exp8_sig16 softfloat_normSubnormalBF16Sig( uint_fast16_t );
+
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
 #define signF32UI( a ) ((bool) ((uint32_t) (a)>>31))

softfloat/source/include/opts-GCC.h

@@ -39,57 +39,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifdef INLINE
 
-#include <stdint.h>
 #include "primitiveTypes.h"
+#include <stdint.h>
 
 #ifdef SOFTFLOAT_BUILTIN_CLZ
 
-INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
-    { return a ? __builtin_clz( a ) - 16 : 16; }
+INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { return a ? __builtin_clz(a) - 16 : 16; }
 #define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16
 
-INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
-    { return a ? __builtin_clz( a ) : 32; }
+INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { return a ? __builtin_clz(a) : 32; }
 #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
 
-INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
-    { return a ? __builtin_clzll( a ) : 64; }
+INLINE uint_fast8_t softfloat_countLeadingZeros64(uint64_t a) { return a ? __builtin_clzll(a) : 64; }
 #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
 
 #endif
 
 #ifdef SOFTFLOAT_INTRINSIC_INT128
 
-INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
-{
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
+    union {
+        unsigned __int128 ui;
+        struct uint128 s;
+    } uZ;
     uZ.ui = (unsigned __int128)a * ((uint_fast64_t)b << 32);
     return uZ.s;
 }
 #define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128
 
-INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
-{
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+INLINE struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b) {
+    union {
+        unsigned __int128 ui;
+        struct uint128 s;
+    } uZ;
     uZ.ui = (unsigned __int128)a * b;
     return uZ.s;
 }
 #define softfloat_mul64To128 softfloat_mul64To128
 
 INLINE
-struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
-{
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
+    union {
+        unsigned __int128 ui;
+        struct uint128 s;
+    } uZ;
     uZ.ui = ((unsigned __int128)a64 << 64 | a0) * b;
     return uZ.s;
 }
 #define softfloat_mul128By32 softfloat_mul128By32
 
 INLINE
-void
- softfloat_mul128To256M(
-     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr )
-{
+void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr) {
     unsigned __int128 z0, mid1, mid, z128;
     z0 = (unsigned __int128)a0 * b0;
     mid1 = (unsigned __int128)a64 * b0;
@@ -111,4 +111,3 @@ void
 #endif
 
 #endif
-

softfloat/source/include/softfloat.h

@@ -81,13 +81,13 @@ enum {
 | Software floating-point exception flags.
 *----------------------------------------------------------------------------*/
 extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags;
-enum {
+typedef enum {
     softfloat_flag_inexact   =  1,
     softfloat_flag_underflow =  2,
     softfloat_flag_overflow  =  4,
     softfloat_flag_infinite  =  8,
     softfloat_flag_invalid   = 16
-};
+} exceptionFlag_t;
 
 /*----------------------------------------------------------------------------
 | Routine to raise any or all of the software floating-point exception flags.
@@ -169,6 +169,13 @@ bool f16_le_quiet( float16_t, float16_t );
 bool f16_lt_quiet( float16_t, float16_t );
 bool f16_isSignalingNaN( float16_t );
 
+/*----------------------------------------------------------------------------
+| 16-bit (brain float 16) floating-point operations.
+*----------------------------------------------------------------------------*/
+float32_t bf16_to_f32( bfloat16_t );
+bfloat16_t f32_to_bf16( float32_t );
+bool bf16_isSignalingNaN( bfloat16_t );
+
 /*----------------------------------------------------------------------------
 | 32-bit (single-precision) floating-point operations.
 *----------------------------------------------------------------------------*/

softfloat/source/include/softfloat_types.h

@@ -48,6 +48,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | (typically 'float' and 'double', and possibly 'long double').
 *----------------------------------------------------------------------------*/
 typedef struct { uint16_t v; } float16_t;
+typedef struct { uint16_t v; } bfloat16_t;
 typedef struct { uint32_t v; } float32_t;
 typedef struct { uint64_t v; } float64_t;
 typedef struct { uint64_t v[2]; } float128_t;

softfloat/source/s_mulAddF32.c

@@ -221,4 +221,3 @@ float32_t
     return uZ.f;
 
 }
-

softfloat/source/s_normSubnormalBF16Sig.c

@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+struct exp8_sig16 softfloat_normSubnormalBF16Sig( uint_fast16_t sig )
+{
+    int_fast8_t shiftDist;
+    struct exp8_sig16 z;
+
+    shiftDist = softfloat_countLeadingZeros16( sig ) - 8;
+    z.exp = 1 - shiftDist;
+    z.sig = sig<<shiftDist;
+    return z;
+
+}
+

softfloat/source/s_roundPackToBF16.c

@@ -0,0 +1,114 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+/** sig last significant bit is sig[7], the 7 LSBs will be used for rounding */
+bfloat16_t
+ softfloat_roundPackToBF16( bool sign, int_fast16_t exp, uint_fast16_t sig )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven;
+    uint_fast8_t roundIncrement, roundBits;
+    bool isTiny;
+    uint_fast16_t uiZ;
+    union ui16_bf16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    roundIncrement = 0x40;
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        roundIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                ? 0x7F
+                : 0;
+    }
+    roundBits = sig & 0x7F;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0xFD <= (unsigned int) exp ) {
+        if ( exp < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                    || (exp < -1) || (sig + roundIncrement < 0x8000);
+            sig = softfloat_shiftRightJam32( sig, -exp );
+            exp = 0;
+            roundBits = sig & 0x7F;
+            if ( isTiny && roundBits ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+        } else if ( (0xFD < exp) || (0x8000 <= sig + roundIncrement) ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            uiZ = packToBF16UI( sign, 0xFF, 0 ) - ! roundIncrement;
+            goto uiZ;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = (sig + roundIncrement)>>7;
+    if ( roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig |= 1;
+            goto packReturn;
+        }
+#endif
+    }
+    sig &= ~(uint_fast16_t) (! (roundBits ^ 0x40) & roundNearEven);
+    if ( ! sig ) exp = 0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ packReturn:
+    uiZ = packToBF16UI( sign, exp, sig );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

src-gen/.gitignore

@@ -0,0 +1,3 @@
+/iss
+/vm
+/sysc

src/iss/arch/hwl.h

@@ -0,0 +1,122 @@
+/*******************************************************************************
+ * Copyright (C) 2022 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_HWL_H
+#define _RISCV_HART_M_P_HWL_H
+
+#include "riscv_hart_common.h"
+#include <iss/vm_types.h>
+
+namespace iss {
+namespace arch {
+
+template <typename BASE> class hwl : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = hwl<BASE>;
+    using reg_t = typename BASE::reg_t;
+
+    hwl(feature_config cfg = feature_config{});
+    virtual ~hwl() = default;
+
+protected:
+    iss::status read_custom_csr_reg(unsigned addr, reg_t& val) override;
+    iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
+};
+
+template <typename BASE>
+inline hwl<BASE>::hwl(feature_config cfg)
+: BASE(cfg) {
+    for(unsigned addr = 0x800; addr < 0x803; ++addr) {
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+    for(unsigned addr = 0x804; addr < 0x807; ++addr) {
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+}
+
+template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t& val) {
+    switch(addr) {
+    case 0x800:
+        val = this->reg.lpstart0;
+        break;
+    case 0x801:
+        val = this->reg.lpend0;
+        break;
+    case 0x802:
+        val = this->reg.lpcount0;
+        break;
+    case 0x804:
+        val = this->reg.lpstart1;
+        break;
+    case 0x805:
+        val = this->reg.lpend1;
+        break;
+    case 0x806:
+        val = this->reg.lpcount1;
+        break;
+    }
+    return iss::Ok;
+}
+
+template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
+    switch(addr) {
+    case 0x800:
+        this->reg.lpstart0 = val;
+        break;
+    case 0x801:
+        this->reg.lpend0 = val;
+        break;
+    case 0x802:
+        this->reg.lpcount0 = val;
+        break;
+    case 0x804:
+        this->reg.lpstart1 = val;
+        break;
+    case 0x805:
+        this->reg.lpend1 = val;
+        break;
+    case 0x806:
+        this->reg.lpcount1 = val;
+        break;
+    }
+    return iss::Ok;
+}
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_HART_M_P_H */

src/iss/arch/riscv_hart_common.h

@@ -35,26 +35,48 @@
 #ifndef _RISCV_HART_COMMON
 #define _RISCV_HART_COMMON
 
-#include "iss/arch_if.h"
 #include <cstdint>
+#include <elfio/elfio.hpp>
+#include <fmt/format.h>
+#include <iss/arch_if.h>
+#include <iss/log_categories.h>
+#include <string>
+#include <unordered_map>
+#include <util/logging.h>
+
+#if defined(__GNUC__)
+#define likely(x) ::__builtin_expect(!!(x), 1)
+#define unlikely(x) ::__builtin_expect(!!(x), 0)
+#else
+#define likely(x) x
+#define unlikely(x) x
+#endif
 
 namespace iss {
 namespace arch {
 
 enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
 
+enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 };
+
 enum riscv_csr {
     /* user-level CSR */
     // User Trap Setup
     ustatus = 0x000,
     uie = 0x004,
     utvec = 0x005,
+    utvt = 0x007, // CLIC
     // User Trap Handling
     uscratch = 0x040,
     uepc = 0x041,
     ucause = 0x042,
     utval = 0x043,
     uip = 0x044,
+    uxnti = 0x045,        // CLIC
+    uintstatus = 0xCB1,   // MRW Current interrupt levels (CLIC) - addr subject to change
+    uintthresh = 0x047,   // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    uscratchcsw = 0x048,  // MRW Conditional scratch swap on priv mode change (CLIC)
+    uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
     // User Floating-Point CSRs
     fflags = 0x001,
     frm = 0x002,
@@ -112,11 +134,10 @@ enum riscv_csr {
     mtval = 0x343,
     mip = 0x344,
     mxnti = 0x345,        // CLIC
-    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintstatus = 0xFB1,   // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintthresh = 0x347,   // MRW Interrupt-level threshold (CLIC) - addr subject to change
     mscratchcsw = 0x348,  // MRW Conditional scratch swap on priv mode change (CLIC)
     mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
-    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
-    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
     // Physical Memory Protection
     pmpcfg0 = 0x3A0,
     pmpcfg1 = 0x3A1,
@@ -164,10 +185,10 @@ enum riscv_csr {
     // Debug Mode Registers
     dcsr = 0x7B0,
     dpc = 0x7B1,
-    dscratch = 0x7B2
+    dscratch0 = 0x7B2,
+    dscratch1 = 0x7B3
 };
 
-
 enum {
     PGSHIFT = 12,
     PTE_PPN_SHIFT = 10,
@@ -185,7 +206,7 @@ enum {
 
 template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
 
-enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4 };
 
 enum {
     ISA_A = 1,
@@ -211,6 +232,17 @@ struct vm_info {
     bool is_active() { return levels; }
 };
 
+struct feature_config {
+    uint64_t clic_base{0xc0000000};
+    unsigned clic_int_ctl_bits{4};
+    unsigned clic_num_irq{16};
+    unsigned clic_num_trigger{0};
+    uint64_t tcm_base{0x10000000};
+    uint64_t tcm_size{0x8000};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
+};
+
 class trap_load_access_fault : public trap_access {
 public:
     trap_load_access_fault(uint64_t badaddr)
@@ -236,7 +268,105 @@ public:
     trap_store_page_fault(uint64_t badaddr)
     : trap_access(15 << 16, badaddr) {}
 };
+
+inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t* const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch(offs & 0x3) {
+    case 0:
+        for(auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + i);
+        break;
+    case 1:
+        for(auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 1 + i);
+        break;
+    case 2:
+        for(auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 2 + i);
+        break;
+    case 3:
+        *data = *(reg_ptr + 3);
+        break;
     }
 }
 
+inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch(offs & 0x3) {
+    case 0:
+        for(auto i = 0U; i < length; ++i)
+            *(reg_ptr + i) = *(data + i);
+        break;
+    case 1:
+        for(auto i = 0U; i < length; ++i)
+            *(reg_ptr + 1 + i) = *(data + i);
+        break;
+    case 2:
+        for(auto i = 0U; i < length; ++i)
+            *(reg_ptr + 2 + i) = *(data + i);
+        break;
+    case 3:
+        *(reg_ptr + 3) = *data;
+        break;
+    }
+}
+struct riscv_hart_common {
+    riscv_hart_common(){};
+    ~riscv_hart_common(){};
+    std::unordered_map<std::string, uint64_t> symbol_table;
+
+    std::unordered_map<std::string, uint64_t> get_sym_table(std::string name) {
+        if(!symbol_table.empty())
+            return symbol_table;
+        FILE* fp = fopen(name.c_str(), "r");
+        if(fp) {
+            std::array<char, 5> buf;
+            auto n = fread(buf.data(), 1, 4, fp);
+            fclose(fp);
+            if(n != 4)
+                throw std::runtime_error("input file has insufficient size");
+            buf[4] = 0;
+            if(strcmp(buf.data() + 1, "ELF") == 0) {
+                // Create elfio reader
+                ELFIO::elfio reader;
+                // Load ELF data
+                if(!reader.load(name))
+                    throw std::runtime_error("could not process elf file");
+                // check elf properties
+                if(reader.get_type() != ET_EXEC)
+                    throw std::runtime_error("wrong elf type in file");
+                if(reader.get_machine() != EM_RISCV)
+                    throw std::runtime_error("wrong elf machine in file");
+                const auto sym_sec = reader.sections[".symtab"];
+                if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
+                    ELFIO::symbol_section_accessor symbols(reader, sym_sec);
+                    auto sym_no = symbols.get_symbols_num();
+                    std::string name;
+                    ELFIO::Elf64_Addr value = 0;
+                    ELFIO::Elf_Xword size = 0;
+                    unsigned char bind = 0;
+                    unsigned char type = 0;
+                    ELFIO::Elf_Half section = 0;
+                    unsigned char other = 0;
+                    for(auto i = 0U; i < sym_no; ++i) {
+                        symbols.get_symbol(i, name, value, size, bind, type, section, other);
+                        if(name != "") {
+                            this->symbol_table[name] = value;
+#ifndef NDEBUG
+                            CPPLOG(DEBUG) << "Found Symbol " << name;
+#endif
+                        }
+                    }
+                }
+                return symbol_table;
+            }
+            throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
+        } else
+            throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    };
+};
+
+} // namespace arch
+} // namespace iss
+
 #endif

src/iss/arch/tgc5c.cpp

@@ -30,28 +30,29 @@
  *
  *******************************************************************************/
 
+// clang-format off
+#include "tgc5c.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgc_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
 
-tgc_c::tgc_c() {
-    reg.icount = 0;
-}
+tgc5c::tgc5c()  = default;
 
-tgc_c::~tgc_c() = default;
+tgc5c::~tgc5c() = default;
 
-void tgc_c::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
+void tgc5c::reset(uint64_t address) {
+    auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
@@ -59,11 +60,11 @@ void tgc_c::reset(uint64_t address) {
     reg.icount=0;
 }
 
-uint8_t *tgc_c::get_regs_base_ptr() {
+uint8_t *tgc5c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
+tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
 }
-
+// clang-format on