fixes templates
This commit is contained in:
parent
551822916c
commit
3fd51cc68c
@ -368,7 +368,7 @@ volatile std::array<bool, 2> dummy = {
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auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
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auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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@ -378,7 +378,7 @@ volatile std::array<bool, 2> dummy = {
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auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
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auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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@ -76,53 +76,7 @@ template <> struct traits<tgc5c> {
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static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
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{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
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/*
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For easy lookup:
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X0 (zero): 0x0000
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X1 (ra) : 0x0004
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X2 (sp) : 0x0008
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X3 (gp) : 0x000c
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X4 (tp) : 0x0010
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X5 (t0) : 0x0014
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X6 (t1) : 0x0018
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X7 (t2) : 0x001c
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X8 (s0/fp): 0x0020
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X9 (s1) : 0x0024
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X10 (a0) : 0x0028
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X11 (a1) : 0x002c
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X12 (a2) : 0x0030
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X13 (a3) : 0x0034
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X14 (a4) : 0x0038
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X15 (a5) : 0x003c
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X16 (a6) : 0x0040
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X17 (a7) : 0x0044
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X18 (s2) : 0x0048
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X19 (s3) : 0x004c
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X20 (s4) : 0x0050
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X21 (s5) : 0x0054
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X22 (s6) : 0x0058
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X23 (s7) : 0x005c
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X24 (s8) : 0x0060
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X25 (s9) : 0x0064
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X26 (s10) : 0x0068
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X27 (s11) : 0x006c
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X28 (t3) : 0x0070
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X29 (t4) : 0x0074
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X30 (t5) : 0x0078
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X31 (t6) : 0x007c
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PC : 0x0080
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NEXT_PC : 0x0084
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PRIV : 0x0085
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DPC : 0x0089
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trap_state : 0x008d
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pending_trap : 0x0091
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icount : 0x0095
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cycle : 0x009d
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instret : 0x00a5
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instruction : 0x00ad
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last_branch : 0x00b1
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*/
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e { FLAGS };
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@ -399,10 +399,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)((int32_t)imm);
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}
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}
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@ -425,10 +425,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)imm ));
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}
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}
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@ -451,15 +451,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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if(rd != 0) {
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*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 ));
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if(rd != 0) {
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*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 ));
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}
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) ));
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this->core.reg.last_branch = 1;
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@ -485,17 +485,17 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t addr_mask = (uint32_t)- 2;
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uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )) & (int64_t)(addr_mask ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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if(rd != 0) {
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*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 ));
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if(rd != 0) {
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*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 ));
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}
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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@ -521,12 +521,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(*(X+rs1) == *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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@ -554,12 +554,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(*(X+rs1) != *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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@ -587,12 +587,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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@ -620,12 +620,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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@ -653,12 +653,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(*(X+rs1) < *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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@ -686,12 +686,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(*(X+rs1) >= *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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@ -719,14 +719,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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int8_t res_27 = super::template read_mem<int8_t>(traits::MEM, load_address);
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if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
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int8_t res = (int8_t)res_27;
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)res;
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}
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}
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@ -750,14 +750,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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int16_t res_28 = super::template read_mem<int16_t>(traits::MEM, load_address);
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if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
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int16_t res = (int16_t)res_28;
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)res;
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}
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}
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@ -781,14 +781,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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int32_t res_29 = super::template read_mem<int32_t>(traits::MEM, load_address);
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if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
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int32_t res = (int32_t)res_29;
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)res;
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}
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}
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@ -812,14 +812,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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uint8_t res_30 = super::template read_mem<uint8_t>(traits::MEM, load_address);
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if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
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uint8_t res = res_30;
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)res;
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}
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}
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@ -843,14 +843,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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uint16_t res_31 = super::template read_mem<uint16_t>(traits::MEM, load_address);
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if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
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uint16_t res = res_31;
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)res;
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}
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}
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@ -874,7 +874,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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@ -901,7 +901,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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@ -928,7 +928,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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@ -955,10 +955,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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if(rd != 0) {
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*(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
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}
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}
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@ -982,11 +982,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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*(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0;
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if(rd != 0) {
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*(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0;
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}
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}
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}
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@ -1009,11 +1009,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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{
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if(rd >= traits::RFS || rs1 >= traits::RFS) {
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raise(0, 2);
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raise(0, 2);
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}
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else {
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if(rd != 0) {
|
||||
*(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1036,10 +1036,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm));
|
||||
}
|
||||
}
|
||||
@ -1063,10 +1063,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm));
|
||||
}
|
||||
}
|
||||
@ -1090,10 +1090,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm));
|
||||
}
|
||||
}
|
||||
@ -1117,10 +1117,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) << shamt;
|
||||
}
|
||||
}
|
||||
@ -1144,10 +1144,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) >> shamt;
|
||||
}
|
||||
}
|
||||
@ -1171,10 +1171,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
|
||||
}
|
||||
}
|
||||
@ -1198,10 +1198,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)(*(X+rs2) ));
|
||||
}
|
||||
}
|
||||
@ -1225,10 +1225,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) - (uint64_t)(*(X+rs2) ));
|
||||
}
|
||||
}
|
||||
@ -1252,11 +1252,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 )));
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )));
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1279,11 +1279,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1306,11 +1306,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1333,10 +1333,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) ^ *(X+rs2);
|
||||
}
|
||||
}
|
||||
@ -1360,11 +1360,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 )));
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )));
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1387,11 +1387,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))));
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ))));
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1414,10 +1414,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) | *(X+rs2);
|
||||
}
|
||||
}
|
||||
@ -1441,10 +1441,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) & *(X+rs2);
|
||||
}
|
||||
}
|
||||
@ -1468,7 +1468,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
{
|
||||
super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ);
|
||||
super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
}
|
||||
break;
|
||||
@ -1482,7 +1482,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
{
|
||||
raise(0, 11);
|
||||
raise(0, 11);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -1495,7 +1495,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
{
|
||||
raise(0, 3);
|
||||
raise(0, 3);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -1542,11 +1542,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
uint32_t res_32 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
uint32_t xrd = res_32;
|
||||
@ -1579,18 +1579,18 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
uint32_t xrd = res_33;
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
if(rs1 != 0) {
|
||||
if(rs1 != 0) {
|
||||
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
}
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = xrd;
|
||||
}
|
||||
}
|
||||
@ -1614,18 +1614,18 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
uint32_t xrd = res_34;
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
if(rs1 != 0) {
|
||||
if(rs1 != 0) {
|
||||
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
}
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = xrd;
|
||||
}
|
||||
}
|
||||
@ -1649,7 +1649,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
@ -1657,7 +1657,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
uint32_t xrd = res_35;
|
||||
super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = xrd;
|
||||
}
|
||||
}
|
||||
@ -1681,17 +1681,17 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
uint32_t xrd = res_36;
|
||||
if(zimm != 0) {
|
||||
if(zimm != 0) {
|
||||
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
}
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = xrd;
|
||||
}
|
||||
}
|
||||
@ -1715,17 +1715,17 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
uint32_t xrd = res_37;
|
||||
if(zimm != 0) {
|
||||
if(zimm != 0) {
|
||||
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
}
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = xrd;
|
||||
}
|
||||
}
|
||||
@ -1769,7 +1769,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
|
||||
@ -1797,7 +1797,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
|
||||
@ -1825,7 +1825,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) );
|
||||
@ -1853,7 +1853,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) );
|
||||
@ -1881,13 +1881,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
int32_t dividend = (int32_t)*(X+rs1);
|
||||
int32_t divisor = (int32_t)*(X+rs2);
|
||||
if(rd != 0) {
|
||||
if(divisor != 0) {
|
||||
if(rd != 0) {
|
||||
if(divisor != 0) {
|
||||
uint32_t MMIN = ((uint32_t)1) << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ));
|
||||
if(*(X+rs1) == MMIN && divisor == - 1) {
|
||||
*(X+rd) = MMIN;
|
||||
@ -1921,10 +1921,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(*(X+rs2) != 0) {
|
||||
if(*(X+rs2) != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) / *(X+rs2);
|
||||
}
|
||||
@ -1955,14 +1955,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(*(X+rs2) != 0) {
|
||||
if(*(X+rs2) != 0) {
|
||||
uint32_t MMIN = (uint32_t)1 << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ));
|
||||
if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = 0;
|
||||
*(X+rd) = 0;
|
||||
}
|
||||
}
|
||||
else {
|
||||
@ -1997,10 +1997,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(*(X+rs2) != 0) {
|
||||
if(*(X+rs2) != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs1) % *(X+rs2);
|
||||
}
|
||||
@ -2030,10 +2030,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(imm) {
|
||||
*(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm ));
|
||||
*(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm ));
|
||||
}
|
||||
else {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -2054,10 +2054,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
|
||||
uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
|
||||
int32_t res_38 = super::template read_mem<int32_t>(traits::MEM, offs);
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
*(X+rd + 8) = (uint32_t)(int32_t)res_38;
|
||||
*(X+rd + 8) = (uint32_t)(int32_t)res_38;
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2077,8 +2077,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
|
||||
super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 + 8));
|
||||
uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
|
||||
super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 + 8));
|
||||
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
||||
}
|
||||
break;
|
||||
@ -2099,10 +2099,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rs1 != 0) {
|
||||
if(rs1 != 0) {
|
||||
*(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int8_t)sext<6>(imm) ));
|
||||
}
|
||||
}
|
||||
@ -2136,7 +2136,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
*(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 ));
|
||||
*(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 ));
|
||||
*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) ));
|
||||
this->core.reg.last_branch = 1;
|
||||
}
|
||||
@ -2158,10 +2158,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((int8_t)sext<6>(imm));
|
||||
}
|
||||
}
|
||||
@ -2183,10 +2183,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
if(imm == 0 || rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
if(imm == 0 || rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
}
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
|
||||
}
|
||||
}
|
||||
@ -2210,7 +2210,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) ));
|
||||
}
|
||||
else {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -2225,7 +2225,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2244,7 +2244,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
*(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
|
||||
*(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2264,11 +2264,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(shamt) {
|
||||
*(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> shamt);
|
||||
*(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> shamt);
|
||||
}
|
||||
else {
|
||||
if(traits::XLEN == 128) {
|
||||
*(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> 64);
|
||||
if(traits::XLEN == 128) {
|
||||
*(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> 64);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -2289,7 +2289,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
*(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) ));
|
||||
*(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) ));
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2308,7 +2308,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
*(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8) ) - (uint64_t)(*(X+rs2 + 8) ));
|
||||
*(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8) ) - (uint64_t)(*(X+rs2 + 8) ));
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2327,7 +2327,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
*(X+rd + 8) = *(X+rd + 8) ^ *(X+rs2 + 8);
|
||||
*(X+rd + 8) = *(X+rd + 8) ^ *(X+rs2 + 8);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2346,7 +2346,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
*(X+rd + 8) = *(X+rd + 8) | *(X+rs2 + 8);
|
||||
*(X+rd + 8) = *(X+rd + 8) | *(X+rs2 + 8);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2365,7 +2365,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
*(X+rd + 8) = *(X+rd + 8) & *(X+rs2 + 8);
|
||||
*(X+rd + 8) = *(X+rd + 8) & *(X+rs2 + 8);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2402,7 +2402,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
if(*(X+rs1 + 8) == 0) {
|
||||
if(*(X+rs1 + 8) == 0) {
|
||||
*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) ));
|
||||
this->core.reg.last_branch = 1;
|
||||
}
|
||||
@ -2424,7 +2424,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
if(*(X+rs1 + 8) != 0) {
|
||||
if(*(X+rs1 + 8) != 0) {
|
||||
*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) ));
|
||||
this->core.reg.last_branch = 1;
|
||||
}
|
||||
@ -2447,10 +2447,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rs1 != 0) {
|
||||
if(rs1 != 0) {
|
||||
*(X+rs1) = *(X+rs1) << nzuimm;
|
||||
}
|
||||
}
|
||||
@ -2472,8 +2472,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS || rd == 0) {
|
||||
raise(0, 2);
|
||||
if(rd >= traits::RFS || rd == 0) {
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
|
||||
@ -2500,10 +2500,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = *(X+rs2);
|
||||
}
|
||||
}
|
||||
@ -2525,7 +2525,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rs1 && rs1 < traits::RFS) {
|
||||
*NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 0x1 );
|
||||
*NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 1 );
|
||||
this->core.reg.last_branch = 1;
|
||||
}
|
||||
else {
|
||||
@ -2563,10 +2563,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rd >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) {
|
||||
if(rd != 0) {
|
||||
*(X+rd) = (uint32_t)((uint64_t)(*(X+rd) ) + (uint64_t)(*(X+rs2) ));
|
||||
}
|
||||
}
|
||||
@ -2588,12 +2588,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rs1 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t new_pc = *(X+rs1);
|
||||
*(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 ));
|
||||
*NEXT_PC = new_pc & (uint32_t)(~ 0x1 );
|
||||
*(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 ));
|
||||
*NEXT_PC = new_pc & (uint32_t)(~ 1 );
|
||||
this->core.reg.last_branch = 1;
|
||||
}
|
||||
}
|
||||
@ -2608,7 +2608,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
raise(0, 3);
|
||||
raise(0, 3);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
@ -2628,7 +2628,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
// execute instruction
|
||||
{
|
||||
if(rs2 >= traits::RFS) {
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
else {
|
||||
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
|
||||
@ -2647,7 +2647,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
{
|
||||
raise(0, 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
break;
|
||||
}// @suppress("No break at end of case")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user