fixes constructor calls of derived riscv_hart classes
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2095ac985b
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@ -46,7 +46,7 @@ public:
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using this_class = hwl<BASE>;
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using reg_t = typename BASE::reg_t;
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hwl();
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hwl(feature_config cfg = feature_config{});
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virtual ~hwl() = default;
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protected:
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@ -56,7 +56,7 @@ protected:
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template<typename BASE>
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inline hwl<BASE>::hwl() {
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inline hwl<BASE>::hwl(feature_config cfg): BASE(cfg) {
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for (unsigned addr = 0x800; addr < 0x803; ++addr){
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this->register_custom_csr_rd(addr);
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this->register_custom_csr_wr(addr);
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@ -226,6 +226,8 @@ struct feature_config {
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unsigned clic_num_trigger{0};
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uint64_t tcm_base{0x10000000};
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uint64_t tcm_size{0x8000};
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uint64_t io_address{0xf0000000};
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uint64_t io_addr_mask{0xf0000000};
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};
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class trap_load_access_fault : public trap_access {
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@ -81,7 +81,7 @@ public:
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using mem_write_f = typename BASE::mem_write_f;
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using phys_addr_t = typename BASE::phys_addr_t;
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wt_cache();
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wt_cache(feature_config cfg = feature_config{});
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virtual ~wt_cache() = default;
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unsigned size{4096};
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@ -103,7 +103,11 @@ protected:
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template<typename BASE>
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inline wt_cache<BASE>::wt_cache() {
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inline wt_cache<BASE>::wt_cache(feature_config cfg)
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:BASE(cfg)
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, io_address{cfg.io_address}
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, io_addr_mask{cfg.io_addr_mask}
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{
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auto cb = base_class::replace_mem_access(
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[this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
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[this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
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