From b7f023756e0f6c0bb3600ffe59dae96026ad1bbe Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Wed, 27 Sep 2023 07:51:49 +0200
Subject: [PATCH] fixes constructor calls of derived riscv_hart classes

---
 src/iss/arch/hwl.h               | 4 ++--
 src/iss/arch/riscv_hart_common.h | 2 ++
 src/iss/arch/wt_cache.h          | 8 ++++++--
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/iss/arch/hwl.h b/src/iss/arch/hwl.h
index 9e954ba..80f0798 100644
--- a/src/iss/arch/hwl.h
+++ b/src/iss/arch/hwl.h
@@ -46,7 +46,7 @@ public:
     using this_class = hwl<BASE>;
     using reg_t = typename BASE::reg_t;
 
-    hwl();
+    hwl(feature_config cfg = feature_config{});
     virtual ~hwl() = default;
 
 protected:
@@ -56,7 +56,7 @@ protected:
 
 
 template<typename BASE>
-inline hwl<BASE>::hwl() {
+inline hwl<BASE>::hwl(feature_config cfg): BASE(cfg) {
     for (unsigned addr = 0x800; addr < 0x803; ++addr){
         this->register_custom_csr_rd(addr);
         this->register_custom_csr_wr(addr);
diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index 45fc000..4125297 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -226,6 +226,8 @@ struct feature_config {
     unsigned clic_num_trigger{0};
     uint64_t tcm_base{0x10000000};
     uint64_t tcm_size{0x8000};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
 };
 
 class trap_load_access_fault : public trap_access {
diff --git a/src/iss/arch/wt_cache.h b/src/iss/arch/wt_cache.h
index 2b3835b..7108b9d 100644
--- a/src/iss/arch/wt_cache.h
+++ b/src/iss/arch/wt_cache.h
@@ -81,7 +81,7 @@ public:
     using mem_write_f = typename BASE::mem_write_f;
     using phys_addr_t = typename BASE::phys_addr_t;
 
-    wt_cache();
+    wt_cache(feature_config cfg = feature_config{});
     virtual ~wt_cache() = default;
 
     unsigned size{4096};
@@ -103,7 +103,11 @@ protected:
 
 
 template<typename BASE>
-inline wt_cache<BASE>::wt_cache() {
+inline wt_cache<BASE>::wt_cache(feature_config cfg)
+:BASE(cfg)
+, io_address{cfg.io_address}
+, io_addr_mask{cfg.io_addr_mask}
+{
     auto cb = base_class::replace_mem_access(
             [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
             [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});