DBT-RISE
/
DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

update to latest coredsl description

Browse Source
master
Eyck Jentzsch 2 years ago
parent 15cd26f800
commit c054d75717
2 changed files with 9 additions and 9 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 2
      incl/iss/arch/tgc_c.h
  2. 16
      src/vm/interp/vm_tgc_c.cpp

2
incl/iss/arch/tgc_c.h
Unescape View File

@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
static constexpr std::array<const char*, 36> reg_aliases{
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;

16
src/vm/interp/vm_tgc_c.cpp
Unescape View File

@ -2001,7 +2001,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t rs1_idx = rs1 + 8;
uint8_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = *(X+rs1_idx) >> shamt;
}
} catch(...){}
@ -2024,11 +2024,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
if(shamt) {
uint32_t rs1_idx = rs1 + 8;
uint8_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> shamt;
}
else if(traits::XLEN == 128) {
uint32_t rs1_idx = rs1 + 8;
uint8_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> 64;
}
} catch(...){}
@ -2051,7 +2051,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t rs1_idx = rs1 + 8;
uint8_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = *(X+rs1_idx) & (int8_t)sext<6>(imm);
}
} catch(...){}
@ -2074,7 +2074,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t rd_idx = rd + 8;
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) - *(X+rs2 + 8);
}
} catch(...){}
@ -2097,7 +2097,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t rd_idx = rd + 8;
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) ^ *(X+rs2 + 8);
}
} catch(...){}
@ -2120,7 +2120,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t rd_idx = rd + 8;
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) | *(X+rs2 + 8);
}
} catch(...){}
@ -2143,7 +2143,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint32_t rd_idx = rd + 8;
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) & *(X+rs2 + 8);
}
} catch(...){}

Write Preview
Loading…
Cancel
Save