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DBT-RISE-TGC
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adds generation if IMEM space

This commit is contained in:
Eyck Jentzsch 2024-02-21 07:08:24 +01:00
parent 9841b16122
commit 119d4a8b43
2 changed files with 2 additions and 2 deletions
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2
gen_input/templates/CORENAME.h.gtl
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@ -109,7 +109,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
enum sreg_flag_e { FLAGS };
enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
${instr.instruction.name} = ${index},<%}%>

2
src/iss/arch/tgc5c.h
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@ -81,7 +81,7 @@ template <> struct traits<tgc5c> {
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, FENCE, RES, CSR };
enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
enum class opcode_e {
LUI = 0,