adapt to privileged spec
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8e4e702cb9
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@ -314,7 +314,6 @@ protected:
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iss::status read_ie(unsigned addr, reg_t &val);
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iss::status write_ie(unsigned addr, reg_t val);
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iss::status read_ip(unsigned addr, reg_t &val);
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iss::status write_ip(unsigned addr, reg_t val);
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iss::status read_hartid(unsigned addr, reg_t &val);
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status write_intstatus(unsigned addr, reg_t val);
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@ -411,7 +410,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
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csr_rd_cb[mtvec] = &this_class::read_tvec;
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csr_wr_cb[mepc] = &this_class::write_epc;
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csr_rd_cb[mip] = &this_class::read_ip;
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csr_wr_cb[mip] = &this_class::write_ip;
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csr_wr_cb[mip] = &this_class::write_null;
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csr_rd_cb[mie] = &this_class::read_ie;
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csr_wr_cb[mie] = &this_class::write_ie;
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csr_rd_cb[mhartid] = &this_class::read_hartid;
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@ -906,14 +905,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
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auto mask = get_irq_mask();
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mask &= 0xf; // only xSIP is writable
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csr[mip] = (csr[mip] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
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csr[addr] = val & get_pc_mask();
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return iss::Ok;
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@ -400,7 +400,6 @@ private:
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iss::status read_ie(unsigned addr, reg_t &val);
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iss::status write_ie(unsigned addr, reg_t val);
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iss::status read_ip(unsigned addr, reg_t &val);
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iss::status write_ip(unsigned addr, reg_t val);
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iss::status read_hartid(unsigned addr, reg_t &val);
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status read_satp(unsigned addr, reg_t &val);
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@ -499,11 +498,11 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
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csr_wr_cb[sepc] = &this_class::write_epc;
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csr_wr_cb[uepc] = &this_class::write_epc;
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csr_rd_cb[mip] = &this_class::read_ip;
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csr_wr_cb[mip] = &this_class::write_ip;
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csr_wr_cb[mip] = &this_class::write_null;
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csr_rd_cb[sip] = &this_class::read_ip;
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csr_wr_cb[sip] = &this_class::write_ip;
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csr_wr_cb[sip] = &this_class::write_null;
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csr_rd_cb[uip] = &this_class::read_ip;
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csr_wr_cb[uip] = &this_class::write_ip;
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csr_wr_cb[uip] = &this_class::write_null;
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csr_rd_cb[mie] = &this_class::read_ie;
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csr_wr_cb[mie] = &this_class::write_ie;
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csr_rd_cb[sie] = &this_class::read_ie;
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@ -959,15 +958,6 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned a
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto mask = get_irq_mask(req_priv_lvl);
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mask &= ~(1 << 7); // MTIP is read only
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csr[mip] = (csr[mip] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned addr, reg_t val) {
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csr[addr] = val & get_pc_mask();
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return iss::Ok;
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@ -329,7 +329,6 @@ protected:
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iss::status read_ie(unsigned addr, reg_t &val);
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iss::status write_ie(unsigned addr, reg_t val);
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iss::status read_ip(unsigned addr, reg_t &val);
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iss::status write_ip(unsigned addr, reg_t val);
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iss::status write_ideleg(unsigned addr, reg_t val);
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iss::status write_edeleg(unsigned addr, reg_t val);
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iss::status read_hartid(unsigned addr, reg_t &val);
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@ -432,7 +431,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
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csr_rd_cb[mtvec] = &this_class::read_tvec;
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csr_wr_cb[mepc] = &this_class::write_epc;
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csr_rd_cb[mip] = &this_class::read_ip;
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csr_wr_cb[mip] = &this_class::write_ip;
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csr_wr_cb[mip] = &this_class::write_null;
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csr_rd_cb[mie] = &this_class::read_ie;
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csr_wr_cb[mie] = &this_class::write_ie;
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csr_rd_cb[mhartid] = &this_class::read_hartid;
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@ -461,7 +460,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
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csr_rd_cb[uie] = &this_class::read_ie;
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csr_wr_cb[uie] = &this_class::write_ie;
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csr_rd_cb[uip] = &this_class::read_ip;
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csr_wr_cb[uip] = &this_class::write_ip;
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csr_wr_cb[uip] = &this_class::write_null;
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csr_wr_cb[uepc] = &this_class::write_epc;
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csr_rd_cb[ustatus] = &this_class::read_status;
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csr_wr_cb[ustatus] = &this_class::write_status;
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@ -1062,14 +1061,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
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auto mask = get_irq_mask((addr >> 8) & 0x3);
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mask &= 0xf; // only xSIP is writable
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csr[mip] = (csr[mip] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ideleg(unsigned addr, reg_t val) {
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auto mask = 0b000100010001; // only U mode supported
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csr[mideleg] = (csr[mideleg] & ~mask) | (val & mask);
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@ -1244,7 +1235,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
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} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
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auto offset = ((addr&0x7fff)-0x40)/4;
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read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
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} else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
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} else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
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auto offset = ((addr&0x7fff)-0x1000)/4;
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read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
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} else {
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@ -1260,10 +1251,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned leng
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clic_cfg_reg&= 0x7e;
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// } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
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// write_uint32(addr, clic_info_reg, data, length);
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} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0xC0)){ // clicinttrig
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} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
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auto offset = ((addr&0x7fff)-0x40)/4;
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write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
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} else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
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} else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
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auto offset = ((addr&0x7fff)-0x1000)/4;
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write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
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}
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