diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h
index d54fd57..f67ad05 100644
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -314,7 +314,6 @@ protected:
iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val);
- iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
@@ -411,7 +410,7 @@ riscv_hart_m_p::riscv_hart_m_p()
csr_rd_cb[mtvec] = &this_class::read_tvec;
csr_wr_cb[mepc] = &this_class::write_epc;
csr_rd_cb[mip] = &this_class::read_ip;
- csr_wr_cb[mip] = &this_class::write_ip;
+ csr_wr_cb[mip] = &this_class::write_null;
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid;
@@ -906,14 +905,6 @@ template iss::status riscv_hart_m_p
return iss::Ok;
}
-template iss::status riscv_hart_m_p::write_ip(unsigned addr, reg_t val) {
- auto mask = get_irq_mask();
- mask &= 0xf; // only xSIP is writable
- csr[mip] = (csr[mip] & ~mask) | (val & mask);
- check_interrupt();
- return iss::Ok;
-}
-
template iss::status riscv_hart_m_p::write_epc(unsigned addr, reg_t val) {
csr[addr] = val & get_pc_mask();
return iss::Ok;
diff --git a/incl/iss/arch/riscv_hart_msu_vp.h b/incl/iss/arch/riscv_hart_msu_vp.h
index 853a4bf..607c952 100644
--- a/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/incl/iss/arch/riscv_hart_msu_vp.h
@@ -400,7 +400,6 @@ private:
iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val);
- iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status read_satp(unsigned addr, reg_t &val);
@@ -499,11 +498,11 @@ riscv_hart_msu_vp::riscv_hart_msu_vp()
csr_wr_cb[sepc] = &this_class::write_epc;
csr_wr_cb[uepc] = &this_class::write_epc;
csr_rd_cb[mip] = &this_class::read_ip;
- csr_wr_cb[mip] = &this_class::write_ip;
+ csr_wr_cb[mip] = &this_class::write_null;
csr_rd_cb[sip] = &this_class::read_ip;
- csr_wr_cb[sip] = &this_class::write_ip;
+ csr_wr_cb[sip] = &this_class::write_null;
csr_rd_cb[uip] = &this_class::read_ip;
- csr_wr_cb[uip] = &this_class::write_ip;
+ csr_wr_cb[uip] = &this_class::write_null;
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[sie] = &this_class::read_ie;
@@ -959,15 +958,6 @@ template iss::status riscv_hart_msu_vp::read_ip(unsigned a
return iss::Ok;
}
-template iss::status riscv_hart_msu_vp::write_ip(unsigned addr, reg_t val) {
- auto req_priv_lvl = (addr >> 8) & 0x3;
- auto mask = get_irq_mask(req_priv_lvl);
- mask &= ~(1 << 7); // MTIP is read only
- csr[mip] = (csr[mip] & ~mask) | (val & mask);
- check_interrupt();
- return iss::Ok;
-}
-
template iss::status riscv_hart_msu_vp::write_epc(unsigned addr, reg_t val) {
csr[addr] = val & get_pc_mask();
return iss::Ok;
diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h
index ae5031f..32f951d 100644
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -329,7 +329,6 @@ protected:
iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val);
- iss::status write_ip(unsigned addr, reg_t val);
iss::status write_ideleg(unsigned addr, reg_t val);
iss::status write_edeleg(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
@@ -432,7 +431,7 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg)
csr_rd_cb[mtvec] = &this_class::read_tvec;
csr_wr_cb[mepc] = &this_class::write_epc;
csr_rd_cb[mip] = &this_class::read_ip;
- csr_wr_cb[mip] = &this_class::write_ip;
+ csr_wr_cb[mip] = &this_class::write_null;
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid;
@@ -461,7 +460,7 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg)
csr_rd_cb[uie] = &this_class::read_ie;
csr_wr_cb[uie] = &this_class::write_ie;
csr_rd_cb[uip] = &this_class::read_ip;
- csr_wr_cb[uip] = &this_class::write_ip;
+ csr_wr_cb[uip] = &this_class::write_null;
csr_wr_cb[uepc] = &this_class::write_epc;
csr_rd_cb[ustatus] = &this_class::read_status;
csr_wr_cb[ustatus] = &this_class::write_status;
@@ -1062,14 +1061,6 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::write_ip(unsigned addr, reg_t val) {
- auto mask = get_irq_mask((addr >> 8) & 0x3);
- mask &= 0xf; // only xSIP is writable
- csr[mip] = (csr[mip] & ~mask) | (val & mask);
- check_interrupt();
- return iss::Ok;
-}
-
template iss::status riscv_hart_mu_p::write_ideleg(unsigned addr, reg_t val) {
auto mask = 0b000100010001; // only U mode supported
csr[mideleg] = (csr[mideleg] & ~mask) | (val & mask);
@@ -1244,7 +1235,7 @@ iss::status riscv_hart_mu_p::read_clic(uint64_t addr, unsigned lengt
} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4;
read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
- } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+ } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
auto offset = ((addr&0x7fff)-0x1000)/4;
read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
} else {
@@ -1260,10 +1251,10 @@ iss::status riscv_hart_mu_p::write_clic(uint64_t addr, unsigned leng
clic_cfg_reg&= 0x7e;
// } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
// write_uint32(addr, clic_info_reg, data, length);
- } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0xC0)){ // clicinttrig
+ } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4;
write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
- } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+ } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
auto offset = ((addr&0x7fff)-0x1000)/4;
write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
}