fixes tohost behavior of SC wrapper and cycle-estimate plugin
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b86d7a517d
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980c8031c3
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@ -101,7 +101,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
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void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
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size_t instr_id = instr_info.instr_id;
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auto entry = delays[instr_id];
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auto& entry = instr_id<delays.size()?delays[instr_id]:illegal_desc;
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if(instr_info.phase_id==PRE_SYNC) {
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if(entry.f)
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current_delay = entry.f(instr_if->get_instr_word());
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@ -110,5 +110,6 @@ void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
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current_delay = instr_if->is_branch_taken()? entry.taken: entry.not_taken;
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if(current_delay>1)
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instr_if->update_last_instr_cycles(current_delay);
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current_delay = 1;
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}
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}
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@ -48,10 +48,10 @@ namespace plugin {
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class cycle_estimate: public vm_plugin {
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struct instr_desc {
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size_t size;
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bool is_branch;
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unsigned not_taken;
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unsigned taken;
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size_t size{0};
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bool is_branch{false};
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unsigned not_taken{1};
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unsigned taken{1};
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std::function<unsigned(uint64_t)> f;
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};
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@ -79,6 +79,7 @@ public:
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private:
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iss::instrumentation_if *instr_if{nullptr};
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uint32_t* reg_base_ptr {nullptr};
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instr_desc illegal_desc{};
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std::vector<instr_desc> delays;
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unsigned current_delay{0};
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struct pair_hash {
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@ -70,14 +70,43 @@ public:
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if (addr.access && iss::access_type::DEBUG)
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return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
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else {
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auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
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// clear MTIP on mtimecmp write
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if (addr.val == 0x2004000) {
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reg_t val;
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this->read_csr(iss::arch::mip, val);
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if (val & (1ULL << 7)) this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
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auto tohost_upper = (sizeof(reg_t) == 4 && addr.val == (this->tohost + 4)) ||
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(sizeof(reg_t) == 8 && addr.val == this->tohost);
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auto tohost_lower = (sizeof(reg_t) == 4 && addr.val == this->tohost) ||
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(sizeof(reg_t)== 64 && addr.val == this->tohost);
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if (tohost_lower || tohost_upper) {
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if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
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switch (hostvar >> 48) {
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case 0:
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if (hostvar != 0x1) {
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SCCINFO(owner->name()) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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} else {
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SCCINFO(owner->name()) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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}
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this->reg.trap_state=std::numeric_limits<uint32_t>::max();
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this->interrupt_sim=hostvar;
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#ifndef WITH_TCC
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throw(iss::simulation_stopped(hostvar));
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#endif
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break;
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default:
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break;
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}
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} else if (tohost_lower)
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to_host_wr_cnt++;
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return iss::Ok;
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} else {
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auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
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// clear MTIP on mtimecmp write
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if (addr.val == 0x2004000) {
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reg_t val;
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this->read_csr(iss::arch::mip, val);
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if (val & (1ULL << 7)) this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
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}
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return res;
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}
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return res;
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}
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}
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@ -146,6 +175,8 @@ public:
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private:
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sysc::tgfs::core_complex *const owner;
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sc_core::sc_event wfi_evt;
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uint64_t hostvar;
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unsigned to_host_wr_cnt = 0;
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};
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}
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#endif /* _SYSC_SC_CORE_ADAPTER_H_ */
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