183 lines
6.8 KiB
C++
183 lines
6.8 KiB
C++
/*
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* sc_core_adapter.h
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*
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* Created on: Jul 5, 2023
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* Author: eyck
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*/
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#ifndef _SYSC_SC_CORE_ADAPTER_H_
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#define _SYSC_SC_CORE_ADAPTER_H_
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#include <scc/report.h>
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#include <util/ities.h>
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#include "sc_core_adapter_if.h"
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#include <iss/iss.h>
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#include <iss/vm_types.h>
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#include <iostream>
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namespace sysc {
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template<typename PLAT>
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class sc_core_adapter : public PLAT, public sc_core_adapter_if {
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public:
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using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
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using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
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using heart_state_t = typename PLAT::hart_state_type;
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sc_core_adapter(sysc::tgfs::core_complex *owner)
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: owner(owner) { }
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iss::arch_if* get_arch_if() override { return this;}
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void set_mhartid(unsigned id) override { PLAT::set_mhartid(id); }
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uint32_t get_mode() override { return this->reg.PRIV; }
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void set_interrupt_execution(bool v) override { this->interrupt_sim = v?1:0; }
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bool get_interrupt_execution() override { return this->interrupt_sim; }
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uint64_t get_state() override { return this->state.mstatus.backing.val; }
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void notify_phase(iss::arch_if::exec_phase p) override {
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if (p == iss::arch_if::ISTART)
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owner->sync(this->instr_if.get_total_cycles());
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}
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iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
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void disass_output(uint64_t pc, const std::string instr) override {
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static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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if (!owner->disass_output(pc, instr)) {
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std::stringstream s;
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s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
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<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
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<< this->reg.icount + this->cycle_offset << "]";
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SCCDEBUG(owner->name())<<"disass: "
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<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
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<< std::setfill(' ') << std::left << instr << s.str();
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}
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};
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iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
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if (addr.access && iss::access_type::DEBUG)
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return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
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else {
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return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
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}
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}
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iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
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if (addr.access && iss::access_type::DEBUG)
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return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
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else {
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auto tohost_upper = (sizeof(reg_t) == 4 && addr.val == (this->tohost + 4)) ||
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(sizeof(reg_t) == 8 && addr.val == this->tohost);
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auto tohost_lower = (sizeof(reg_t) == 4 && addr.val == this->tohost) ||
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(sizeof(reg_t)== 64 && addr.val == this->tohost);
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if (tohost_lower || tohost_upper) {
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if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
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switch (hostvar >> 48) {
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case 0:
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if (hostvar != 0x1) {
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SCCINFO(owner->name()) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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} else {
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SCCINFO(owner->name()) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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}
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this->reg.trap_state=std::numeric_limits<uint32_t>::max();
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this->interrupt_sim=hostvar;
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#ifndef WITH_TCC
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throw(iss::simulation_stopped(hostvar));
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#endif
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break;
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default:
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break;
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}
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} else if (tohost_lower)
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to_host_wr_cnt++;
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return iss::Ok;
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} else {
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auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
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// clear MTIP on mtimecmp write
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if (addr.val == 0x2004000) {
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reg_t val;
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this->read_csr(iss::arch::mip, val);
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if (val & (1ULL << 7)) this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
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}
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return res;
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}
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}
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}
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iss::status read_csr(unsigned addr, reg_t &val) override {
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#ifndef CWR_SYSTEMC
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if((addr==iss::arch::time || addr==iss::arch::timeh) && owner->mtime_o.get_interface(0)){
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uint64_t time_val;
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bool ret = owner->mtime_o->nb_peek(time_val);
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if (addr == iss::arch::time) {
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val = static_cast<reg_t>(time_val);
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} else if (addr == iss::arch::timeh) {
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if (sizeof(reg_t) != 4) return iss::Err;
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val = static_cast<reg_t>(time_val >> 32);
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}
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return ret?iss::Ok:iss::Err;
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#else
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if((addr==iss::arch::time || addr==iss::arch::timeh)){
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uint64_t time_val = owner->mtime_i.read();
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if (addr == iss::arch::time) {
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val = static_cast<reg_t>(time_val);
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} else if (addr == iss::arch::timeh) {
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if (sizeof(reg_t) != 4) return iss::Err;
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val = static_cast<reg_t>(time_val >> 32);
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}
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return iss::Ok;
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#endif
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} else {
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return PLAT::read_csr(addr, val);
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}
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}
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void wait_until(uint64_t flags) override {
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SCCDEBUG(owner->name()) << "Sleeping until interrupt";
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while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
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sc_core::wait(wfi_evt);
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}
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PLAT::wait_until(flags);
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}
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void local_irq(short id, bool value) override {
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reg_t mask = 0;
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switch (id) {
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case 3: // SW
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mask = 1 << 3;
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break;
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case 7: // timer
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mask = 1 << 7;
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break;
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case 11: // external
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mask = 1 << 11;
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break;
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default:
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if(id>15) mask = 1 << id;
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break;
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}
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if (value) {
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this->csr[iss::arch::mip] |= mask;
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wfi_evt.notify();
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} else
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this->csr[iss::arch::mip] &= ~mask;
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this->check_interrupt();
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if(value)
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SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
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}
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private:
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sysc::tgfs::core_complex *const owner;
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sc_core::sc_event wfi_evt;
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uint64_t hostvar;
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unsigned to_host_wr_cnt = 0;
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};
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}
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#endif /* _SYSC_SC_CORE_ADAPTER_H_ */
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