DBT-RISE/DBT-RISE-TGC
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removes setting of NEXT_PC to max if trap

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Eyck-Alexander Jentzsch 2024-07-18 11:37:53 +02:00
parent 2ec7ea4b41
commit 8361f88718
2 changed files with 0 additions and 2 deletions
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1
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -106,7 +106,6 @@ protected:
inline void raise(uint16_t trap_id, uint16_t cause){
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
this->core.reg.trap_state = trap_val;
this->template get_reg<uint${addrDataWidth}_t>(traits::NEXT_PC) = std::numeric_limits<uint${addrDataWidth}_t>::max();
}
inline void leave(unsigned lvl){

1
src/vm/interp/vm_tgc5c.cpp
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@ -102,7 +102,6 @@ protected:
inline void raise(uint16_t trap_id, uint16_t cause){
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
this->core.reg.trap_state = trap_val;
this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
}
inline void leave(unsigned lvl){