DBT-RISE/DBT-RISE-TGC
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removes leftover gen_sync in asmjit

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Eyck-Alexander Jentzsch 2024-07-17 22:39:12 +02:00
parent b24965d321
commit 2ec7ea4b41
2 changed files with 0 additions and 2 deletions
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1
gen_input/templates/asmjit/CORENAME.cpp.gtl
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@ -328,7 +328,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
cc.bind(jh.trap_entry);
this->write_back(jh);
this->gen_sync(jh, POST_SYNC, -1);
x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));

1
src/vm/asmjit/vm_tgc5c.cpp
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@ -4851,7 +4851,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
cc.bind(jh.trap_entry);
this->write_back(jh);
this->gen_sync(jh, POST_SYNC, -1);
x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));