corrects gen_sync update order, improves illegal instruction
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244bf6d2f2
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b24965d321
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@ -170,13 +170,13 @@ private:
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auto cur_pc_val = this->gen_const(32,pc.val);
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pc=pc+ ${instr.length/8};
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this->gen_set_pc(pc, traits::NEXT_PC);
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this->set_tval(PC);
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this->set_tval(instr);
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/*generate behavior*/
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<%instr.behavior.eachLine{%>${it}
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<%}%>
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this->gen_sync(POST_SYNC, ${idx});
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this->gen_instr_epilogue(bb);
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this->gen_sync(POST_SYNC, ${idx});
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this->builder.CreateBr(bb);
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return returnValue;
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}
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@ -185,6 +185,15 @@ private:
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* end opcode definitions
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****************************************************************************/
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std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
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if(this->disass_enabled){
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auto mnemonic = std::string("illegal_instruction");
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std::vector<Value*> args {
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this->core_ptr,
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this->gen_const(64, pc.val),
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this->builder.CreateGlobalStringPtr(mnemonic),
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};
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this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
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}
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this->gen_sync(iss::PRE_SYNC, instr_descr.size());
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this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
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get_reg_ptr(traits::PC), true);
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@ -193,6 +202,7 @@ private:
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this->gen_const(64U, 1)),
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get_reg_ptr(traits::ICOUNT), true);
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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this->set_tval(instr);
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this->gen_raise_trap(0, 2); // illegal instruction trap
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this->gen_sync(iss::POST_SYNC, instr_descr.size());
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this->gen_instr_epilogue(this->leave_blk);
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@ -341,7 +351,6 @@ inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
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template <typename ARCH>
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void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
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this->builder.SetInsertPoint(trap_blk);
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this->gen_sync(POST_SYNC, -1); //TODO get right InstrId
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auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
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this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
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get_reg_ptr(traits::LAST_BRANCH), false);
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