splits bus into 2 sockets for i/dbus
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916de2a26d
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d330307ed5
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@ -14,9 +14,11 @@ puts "instantiate testbench elements"
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::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
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{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::set_bounds i_Bus 700 300 100 400
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::pct::create_connection C_init i_core_complex/initiator i_Bus/i_core_complex_initiator
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::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
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::pct::create_connection C_targ i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
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::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
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::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
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::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
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::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
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::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
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puts "instantiating clock manager"
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set clock "Clk"
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@ -44,7 +46,8 @@ puts "connecting reset/clock"
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puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
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::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
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::pct::set_address $hardware/i_${top_design_name}/initiator:i_Memory_Generic/MEM 0x0
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::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
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::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
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::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
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@ -330,6 +330,7 @@ SC_HAS_PROCESS(core_complex);// NOLINT
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#ifndef CWR_SYSTEMC
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core_complex::core_complex(sc_module_name const& name)
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: sc_module(name)
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, fetch_lut(tlm_dmi_ext())
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, read_lut(tlm_dmi_ext())
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, write_lut(tlm_dmi_ext())
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{
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@ -339,7 +340,13 @@ core_complex::core_complex(sc_module_name const& name)
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void core_complex::init(){
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trc=new core_trace();
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initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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auto lut_entry = fetch_lut.getEntry(start);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
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fetch_lut.removeEntry(lut_entry);
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}
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});
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dbus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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auto lut_entry = read_lut.getEntry(start);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
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read_lut.removeEntry(lut_entry);
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@ -516,13 +523,15 @@ void core_complex::run() {
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}
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bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
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auto lut_entry = read_lut.getEntry(addr);
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auto& dmi_lut = is_fetch?fetch_lut:read_lut;
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auto lut_entry = dmi_lut.getEntry(addr);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
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auto offset = addr - lut_entry.get_start_address();
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std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
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quantum_keeper.inc(lut_entry.get_read_latency());
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return true;
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} else {
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auto& sckt = is_fetch? ibus : dbus;
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tlm::tlm_generic_payload gp;
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(addr);
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@ -537,7 +546,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
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auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
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gp.set_extension(preExt);
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}
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initiator->b_transport(gp, delay);
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sckt->b_transport(gp, delay);
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quantum_keeper.set(delay);
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SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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@ -547,9 +556,9 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(addr);
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tlm_dmi_ext dmi_data;
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if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
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if (sckt->get_direct_mem_ptr(gp, dmi_data)) {
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if (dmi_data.is_read_allowed())
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read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
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dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(),
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dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
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}
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}
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@ -579,7 +588,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
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auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
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gp.set_extension(preExt);
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}
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initiator->b_transport(gp, delay);
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dbus->b_transport(gp, delay);
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quantum_keeper.set(delay);
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SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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@ -589,7 +598,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(addr);
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tlm_dmi_ext dmi_data;
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if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
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if (dbus->get_direct_mem_ptr(gp, dmi_data)) {
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if (dmi_data.is_write_allowed())
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write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
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dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
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@ -606,7 +615,7 @@ bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const d
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gp.set_data_ptr(data);
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gp.set_data_length(length);
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gp.set_streaming_width(length);
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return initiator->transport_dbg(gp) == length;
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return dbus->transport_dbg(gp) == length;
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}
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bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
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@ -618,7 +627,7 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
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gp.set_data_ptr(write_buf.data());
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gp.set_data_length(length);
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gp.set_streaming_width(length);
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return initiator->transport_dbg(gp) == length;
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return dbus->transport_dbg(gp) == length;
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}
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} /* namespace SiFive */
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} /* namespace sysc */
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@ -40,8 +40,10 @@
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#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
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#ifdef CWR_SYSTEMC
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#include <scmlinc/scml_property.h>
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#define SOCKET_WIDTH 32
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#else
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#include <cci_configuration>
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#define SOCKET_WIDTH scc::LT
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#endif
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#include <tlm>
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#include <tlm_utils/tlm_quantumkeeper.h>
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@ -69,7 +71,9 @@ struct core_trace;
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class core_complex : public sc_core::sc_module, public scc::traceable {
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public:
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator{"intor"};
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};
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sc_core::sc_in<bool> rst_i{"rst_i"};
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@ -141,6 +145,7 @@ public:
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, dump_ir{"dump_ir", false}
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, mhartid{"mhartid", 0}
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, plugins{"plugins", ""}
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, fetch_lut(tlm_dmi_ext())
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, read_lut(tlm_dmi_ext())
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, write_lut(tlm_dmi_ext())
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{
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@ -185,7 +190,7 @@ protected:
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void ext_irq_cb();
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void local_irq_cb();
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uint64_t last_sync_cycle = 0;
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util::range_lut<tlm_dmi_ext> read_lut, write_lut;
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util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
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tlm_utils::tlm_quantumkeeper quantum_keeper;
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std::vector<uint8_t> write_buf;
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core_wrapper* cpu{nullptr};
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