From d330307ed5fe7cae9c01bd875194e31f28cbe6d1 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Thu, 4 May 2023 21:59:31 +0200 Subject: [PATCH] splits bus into 2 sockets for i/dbus --- contrib/tgc_import_tb.tcl | 11 +++++++---- src/sysc/core_complex.cpp | 27 ++++++++++++++++++--------- src/sysc/core_complex.h | 9 +++++++-- 3 files changed, 32 insertions(+), 15 deletions(-) diff --git a/contrib/tgc_import_tb.tcl b/contrib/tgc_import_tb.tcl index 6a7ce1d..fb44353 100644 --- a/contrib/tgc_import_tb.tcl +++ b/contrib/tgc_import_tb.tcl @@ -14,9 +14,11 @@ puts "instantiate testbench elements" ::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \ { common_configuration:BackBone:/advanced/num_resources_per_target:1 } ::pct::set_bounds i_Bus 700 300 100 400 -::pct::create_connection C_init i_core_complex/initiator i_Bus/i_core_complex_initiator -::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10 -::pct::create_connection C_targ i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM +::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus +::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10 +::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus +::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10 +::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM puts "instantiating clock manager" set clock "Clk" @@ -44,7 +46,8 @@ puts "connecting reset/clock" puts "setting parameters for DBT-RISE-TGC/Bus and memory components" ::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name} -::pct::set_address $hardware/i_${top_design_name}/initiator:i_Memory_Generic/MEM 0x0 +::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0 +::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0 ::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 } ::pct::set_main_configuration Default {{#include } {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}} diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index 75da28e..9bb81cf 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -330,6 +330,7 @@ SC_HAS_PROCESS(core_complex);// NOLINT #ifndef CWR_SYSTEMC core_complex::core_complex(sc_module_name const& name) : sc_module(name) +, fetch_lut(tlm_dmi_ext()) , read_lut(tlm_dmi_ext()) , write_lut(tlm_dmi_ext()) { @@ -339,7 +340,13 @@ core_complex::core_complex(sc_module_name const& name) void core_complex::init(){ trc=new core_trace(); - initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void { + ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void { + auto lut_entry = fetch_lut.getEntry(start); + if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) { + fetch_lut.removeEntry(lut_entry); + } + }); + dbus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void { auto lut_entry = read_lut.getEntry(start); if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) { read_lut.removeEntry(lut_entry); @@ -516,13 +523,15 @@ void core_complex::run() { } bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) { - auto lut_entry = read_lut.getEntry(addr); + auto& dmi_lut = is_fetch?fetch_lut:read_lut; + auto lut_entry = dmi_lut.getEntry(addr); if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) { auto offset = addr - lut_entry.get_start_address(); std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data); quantum_keeper.inc(lut_entry.get_read_latency()); return true; } else { + auto& sckt = is_fetch? ibus : dbus; tlm::tlm_generic_payload gp; gp.set_command(tlm::TLM_READ_COMMAND); gp.set_address(addr); @@ -537,7 +546,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this); gp.set_extension(preExt); } - initiator->b_transport(gp, delay); + sckt->b_transport(gp, delay); quantum_keeper.set(delay); SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data); if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) { @@ -547,9 +556,9 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, gp.set_command(tlm::TLM_READ_COMMAND); gp.set_address(addr); tlm_dmi_ext dmi_data; - if (initiator->get_direct_mem_ptr(gp, dmi_data)) { + if (sckt->get_direct_mem_ptr(gp, dmi_data)) { if (dmi_data.is_read_allowed()) - read_lut.addEntry(dmi_data, dmi_data.get_start_address(), + dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1); } } @@ -579,7 +588,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this); gp.set_extension(preExt); } - initiator->b_transport(gp, delay); + dbus->b_transport(gp, delay); quantum_keeper.set(delay); SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data); if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) { @@ -589,7 +598,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons gp.set_command(tlm::TLM_READ_COMMAND); gp.set_address(addr); tlm_dmi_ext dmi_data; - if (initiator->get_direct_mem_ptr(gp, dmi_data)) { + if (dbus->get_direct_mem_ptr(gp, dmi_data)) { if (dmi_data.is_write_allowed()) write_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1); @@ -606,7 +615,7 @@ bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const d gp.set_data_ptr(data); gp.set_data_length(length); gp.set_streaming_width(length); - return initiator->transport_dbg(gp) == length; + return dbus->transport_dbg(gp) == length; } bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) { @@ -618,7 +627,7 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t * gp.set_data_ptr(write_buf.data()); gp.set_data_length(length); gp.set_streaming_width(length); - return initiator->transport_dbg(gp) == length; + return dbus->transport_dbg(gp) == length; } } /* namespace SiFive */ } /* namespace sysc */ diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h index 9b53397..8c6680b 100644 --- a/src/sysc/core_complex.h +++ b/src/sysc/core_complex.h @@ -40,8 +40,10 @@ #include #ifdef CWR_SYSTEMC #include +#define SOCKET_WIDTH 32 #else #include +#define SOCKET_WIDTH scc::LT #endif #include #include @@ -69,7 +71,9 @@ struct core_trace; class core_complex : public sc_core::sc_module, public scc::traceable { public: - tlm::scc::initiator_mixin> initiator{"intor"}; + tlm::scc::initiator_mixin> ibus{"ibus"}; + + tlm::scc::initiator_mixin> dbus{"dbus"}; sc_core::sc_in rst_i{"rst_i"}; @@ -141,6 +145,7 @@ public: , dump_ir{"dump_ir", false} , mhartid{"mhartid", 0} , plugins{"plugins", ""} + , fetch_lut(tlm_dmi_ext()) , read_lut(tlm_dmi_ext()) , write_lut(tlm_dmi_ext()) { @@ -185,7 +190,7 @@ protected: void ext_irq_cb(); void local_irq_cb(); uint64_t last_sync_cycle = 0; - util::range_lut read_lut, write_lut; + util::range_lut fetch_lut, read_lut, write_lut; tlm_utils::tlm_quantumkeeper quantum_keeper; std::vector write_buf; core_wrapper* cpu{nullptr};