Add a new LOG macro in SCC to avoid conflicts with other libraries.
This commit is contained in:
parent
1e6a0086e9
commit
8aed551813
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@ -600,7 +600,7 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
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auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
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pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
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if(res != iss::Ok)
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LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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}
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}
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for(const auto sec : reader.sections) {
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@ -654,11 +654,11 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
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const unsigned length, uint8_t* const data) {
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#ifndef NDEBUG
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if(access && iss::access_type::DEBUG) {
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LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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} else if(access && iss::access_type::FETCH) {
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LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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} else {
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LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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}
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#endif
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try {
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@ -740,23 +740,23 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
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const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
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switch(length) {
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case 8:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 4:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 2:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 1:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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default:
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LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
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}
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#endif
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try {
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@ -808,7 +808,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
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case 0x10023000: // UART1 base, TXFIFO reg
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uart_buf << (char)data[0];
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if(((char)data[0]) == '\n' || data[0] == 0) {
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// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
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// CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
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// '"<<uart_buf.str()<<"'";
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std::cout << uart_buf.str();
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uart_buf.str("");
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@ -1108,7 +1108,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
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// TODO remove UART, Peripherals should not be part of the ISS
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case 0xFFFF0000: // UART0 base, TXFIFO reg
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if(((char)data[0]) == '\n' || data[0] == 0) {
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LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
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CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
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uart_buf.str("");
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} else if(((char)data[0]) != '\r')
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uart_buf << (char)data[0];
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@ -1128,10 +1128,10 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
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switch(hostvar >> 48) {
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case 0:
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if(hostvar != 0x1) {
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LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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} else {
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LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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}
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this->reg.trap_state = std::numeric_limits<uint32_t>::max();
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@ -1143,7 +1143,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
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case 0x0101: {
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char c = static_cast<char>(hostvar & 0xff);
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if(c == '\n' || c == 0) {
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LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
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CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
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uart_buf.str("");
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} else
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uart_buf << c;
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@ -591,7 +591,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
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auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
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pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
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if(res != iss::Ok)
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LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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}
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}
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for(const auto sec : reader.sections) {
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@ -632,11 +632,11 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
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const unsigned length, uint8_t* const data) {
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#ifndef NDEBUG
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if(access && iss::access_type::DEBUG) {
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LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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} else if(access && iss::access_type::FETCH) {
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LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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} else {
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LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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}
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#endif
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try {
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@ -726,23 +726,23 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
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const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
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switch(length) {
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case 8:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 4:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 2:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 1:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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default:
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LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
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}
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#endif
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try {
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@ -787,7 +787,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
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case 0x10023000: // UART1 base, TXFIFO reg
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uart_buf << (char)data[0];
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if(((char)data[0]) == '\n' || data[0] == 0) {
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// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
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// CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
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// '"<<uart_buf.str()<<"'";
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std::cout << uart_buf.str();
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uart_buf.str("");
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@ -1083,7 +1083,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
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switch(paddr.val) {
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case 0xFFFF0000: // UART0 base, TXFIFO reg
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if(((char)data[0]) == '\n' || data[0] == 0) {
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LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
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CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
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uart_buf.str("");
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} else if(((char)data[0]) != '\r')
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uart_buf << (char)data[0];
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@ -1103,10 +1103,10 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
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switch(hostvar >> 48) {
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case 0:
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if(hostvar != 0x1) {
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LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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} else {
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LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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}
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this->reg.trap_state = std::numeric_limits<uint32_t>::max();
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@ -1118,7 +1118,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
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case 0x0101: {
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char c = static_cast<char>(hostvar & 0xff);
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if(c == '\n' || c == 0) {
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LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
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CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
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uart_buf.str("");
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} else
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uart_buf << c;
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@ -678,7 +678,7 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
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auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
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pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
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if(res != iss::Ok)
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LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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}
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}
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for(const auto sec : reader.sections) {
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@ -818,11 +818,11 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
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const unsigned length, uint8_t* const data) {
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#ifndef NDEBUG
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if(access && iss::access_type::DEBUG) {
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LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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} else if(is_fetch(access)) {
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LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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} else {
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LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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}
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#endif
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try {
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@ -913,23 +913,23 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
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const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
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switch(length) {
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case 8:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 4:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 2:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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case 1:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
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<< std::hex << addr;
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break;
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default:
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LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
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CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
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}
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#endif
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try {
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@ -990,7 +990,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
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case 0x10023000: // UART1 base, TXFIFO reg
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uart_buf << (char)data[0];
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if(((char)data[0]) == '\n' || data[0] == 0) {
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// LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send
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// CPPLOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send
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// '"<<uart_buf.str()<<"'";
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std::cout << uart_buf.str();
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uart_buf.str("");
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@ -1326,7 +1326,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
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// TODO remove UART, Peripherals should not be part of the ISS
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case 0xFFFF0000: // UART0 base, TXFIFO reg
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if(((char)data[0]) == '\n' || data[0] == 0) {
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LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
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CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
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uart_buf.str("");
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} else if(((char)data[0]) != '\r')
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uart_buf << (char)data[0];
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@ -1346,10 +1346,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
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switch(hostvar >> 48) {
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case 0:
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if(hostvar != 0x1) {
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LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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} else {
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LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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}
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this->reg.trap_state = std::numeric_limits<uint32_t>::max();
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@ -1361,7 +1361,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
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case 0x0101: {
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char c = static_cast<char>(hostvar & 0xff);
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if(c == '\n' || c == 0) {
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LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
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CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
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uart_buf.str("");
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} else
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uart_buf << c;
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@ -174,7 +174,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
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LOG(TRACE) << "reading target registers";
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CPPLOG(TRACE) << "reading target registers";
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// return idx<0?:;
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data.clear();
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avail.clear();
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@ -328,9 +328,9 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
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auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
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auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
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target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
|
||||
LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
|
||||
CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
|
||||
<< std::dec;
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Ok;
|
||||
}
|
||||
}
|
||||
|
@ -345,13 +345,13 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
|
|||
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
|
||||
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
|
||||
if(handle) {
|
||||
LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
|
||||
CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
|
||||
// TODO: check length of addr range
|
||||
target_adapter_base::bp_lut.removeEntry(handle);
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Ok;
|
||||
}
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Err;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -61,7 +61,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
|
|||
try {
|
||||
auto root = YAML::LoadAll(is);
|
||||
if(root.size() != 1) {
|
||||
LOG(ERR) << "Too many root nodes in YAML file " << config_file_name;
|
||||
CPPLOG(ERR) << "Too many root nodes in YAML file " << config_file_name;
|
||||
}
|
||||
for(auto p : root[0]) {
|
||||
auto isa_subset = p.first;
|
||||
|
@ -87,11 +87,11 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
|
|||
}
|
||||
}
|
||||
} catch(YAML::ParserException& e) {
|
||||
LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
LOG(ERR) << "Could not open input file " << config_file_name;
|
||||
CPPLOG(ERR) << "Could not open input file " << config_file_name;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -47,7 +47,7 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
|
|||
try {
|
||||
auto root = YAML::LoadAll(is);
|
||||
if(root.size() != 1) {
|
||||
LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
|
||||
CPPLOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
|
||||
}
|
||||
for(auto p : root[0]) {
|
||||
auto isa_subset = p.first;
|
||||
|
@ -69,10 +69,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
|
|||
}
|
||||
rep_counts.resize(delays.size());
|
||||
} catch(YAML::ParserException& e) {
|
||||
LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
}
|
||||
} else {
|
||||
LOG(ERR) << "Could not open input file " << config_file_name;
|
||||
CPPLOG(ERR) << "Could not open input file " << config_file_name;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -81,7 +81,7 @@ iss::plugin::instruction_count::~instruction_count() {
|
|||
size_t idx = 0;
|
||||
for(auto it : delays) {
|
||||
if(rep_counts[idx] > 0 && it.instr_name.find("__" != 0))
|
||||
LOG(INFO) << it.instr_name << ";" << rep_counts[idx];
|
||||
CPPLOG(INFO) << it.instr_name << ";" << rep_counts[idx];
|
||||
idx++;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -137,11 +137,11 @@ int main(int argc, char* argv[]) {
|
|||
std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>(), &semihosting_cb);
|
||||
}
|
||||
if(!cpu) {
|
||||
LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
|
||||
CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
|
||||
return 127;
|
||||
}
|
||||
if(!vm) {
|
||||
LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
|
||||
CPPLOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
|
||||
return 127;
|
||||
}
|
||||
if(clim.count("plugin")) {
|
||||
|
@ -177,7 +177,7 @@ int main(int argc, char* argv[]) {
|
|||
} else
|
||||
#endif
|
||||
{
|
||||
LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
|
||||
CPPLOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
|
||||
return 127;
|
||||
}
|
||||
}
|
||||
|
@ -215,7 +215,7 @@ int main(int argc, char* argv[]) {
|
|||
auto cycles = clim["instructions"].as<uint64_t>();
|
||||
res = vm->start(cycles, dump);
|
||||
} catch(std::exception& e) {
|
||||
LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
|
||||
CPPLOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
|
||||
res = 2;
|
||||
}
|
||||
// cleanup to let plugins report of needed
|
||||
|
|
Loading…
Reference in New Issue