diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 99a7f06..1a3d84b 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -600,7 +600,7 @@ template std::pair riscv_hart_m auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if(res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); + CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { @@ -654,11 +654,11 @@ iss::status riscv_hart_m_p::read(const address_type type, const acce const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { - LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; } else if(access && iss::access_type::FETCH) { - LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { - LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; } #endif try { @@ -740,23 +740,23 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; default: - LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; + CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { @@ -808,7 +808,7 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; if(((char)data[0]) == '\n' || data[0] == 0) { - // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send + // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // '"<::write_mem(phys_addr_t paddr, unsigned le // TODO remove UART, Peripherals should not be part of the ISS case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; @@ -1128,10 +1128,10 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { - LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { - LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); @@ -1143,7 +1143,7 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { - LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else uart_buf << c; diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 4329160..7384abc 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -591,7 +591,7 @@ template std::pair riscv_hart_msu_vp::load auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if(res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); + CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { @@ -632,11 +632,11 @@ iss::status riscv_hart_msu_vp::read(const address_type type, const access_ const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { - LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; } else if(access && iss::access_type::FETCH) { - LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { - LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; } #endif try { @@ -726,23 +726,23 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; default: - LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; + CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { @@ -787,7 +787,7 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; if(((char)data[0]) == '\n' || data[0] == 0) { - // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send + // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // '"< iss::status riscv_hart_msu_vp::write_mem(phys_add switch(paddr.val) { case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; @@ -1103,10 +1103,10 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { - LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { - LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); @@ -1118,7 +1118,7 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { - LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else uart_buf << c; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 362fece..9d5355b 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -678,7 +678,7 @@ template std::pair riscv_hart_m auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if(res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); + CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { @@ -818,11 +818,11 @@ iss::status riscv_hart_mu_p::read(const address_type type, const acc const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { - LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; } else if(is_fetch(access)) { - LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { - LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; } #endif try { @@ -913,23 +913,23 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; default: - LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; + CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { @@ -990,7 +990,7 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; if(((char)data[0]) == '\n' || data[0] == 0) { - // LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send + // CPPLOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send // '"<::write_mem(phys_addr_t paddr, unsigned l // TODO remove UART, Peripherals should not be part of the ISS case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; @@ -1346,10 +1346,10 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { - LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { - LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); @@ -1361,7 +1361,7 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { - LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else uart_buf << c; diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h index 6a2a527..ac85a67 100644 --- a/src/iss/debugger/riscv_target_adapter.h +++ b/src/iss/debugger/riscv_target_adapter.h @@ -174,7 +174,7 @@ template status riscv_target_adapter::current_thread_query } template status riscv_target_adapter::read_registers(std::vector& data, std::vector& avail) { - LOG(TRACE) << "reading target registers"; + CPPLOG(TRACE) << "reading target registers"; // return idx<0?:; data.clear(); avail.clear(); @@ -328,9 +328,9 @@ template status riscv_target_adapter::add_break(break_type auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length}); target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val); - LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val + CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val << std::dec; - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Ok; } } @@ -345,13 +345,13 @@ template status riscv_target_adapter::remove_break(break_t auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val); if(handle) { - LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec; + CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec; // TODO: check length of addr range target_adapter_base::bp_lut.removeEntry(handle); - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Ok; } - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Err; } } diff --git a/src/iss/plugin/cycle_estimate.cpp b/src/iss/plugin/cycle_estimate.cpp index 69e466a..463e2fa 100644 --- a/src/iss/plugin/cycle_estimate.cpp +++ b/src/iss/plugin/cycle_estimate.cpp @@ -61,7 +61,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& try { auto root = YAML::LoadAll(is); if(root.size() != 1) { - LOG(ERR) << "Too many root nodes in YAML file " << config_file_name; + CPPLOG(ERR) << "Too many root nodes in YAML file " << config_file_name; } for(auto p : root[0]) { auto isa_subset = p.first; @@ -87,11 +87,11 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& } } } catch(YAML::ParserException& e) { - LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); + CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); return false; } } else { - LOG(ERR) << "Could not open input file " << config_file_name; + CPPLOG(ERR) << "Could not open input file " << config_file_name; return false; } } diff --git a/src/iss/plugin/instruction_count.cpp b/src/iss/plugin/instruction_count.cpp index bb47e53..000712f 100644 --- a/src/iss/plugin/instruction_count.cpp +++ b/src/iss/plugin/instruction_count.cpp @@ -47,7 +47,7 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name) try { auto root = YAML::LoadAll(is); if(root.size() != 1) { - LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name; + CPPLOG(ERR) << "Too many rro nodes in YAML file " << config_file_name; } for(auto p : root[0]) { auto isa_subset = p.first; @@ -69,10 +69,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name) } rep_counts.resize(delays.size()); } catch(YAML::ParserException& e) { - LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); + CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); } } else { - LOG(ERR) << "Could not open input file " << config_file_name; + CPPLOG(ERR) << "Could not open input file " << config_file_name; } } } @@ -81,7 +81,7 @@ iss::plugin::instruction_count::~instruction_count() { size_t idx = 0; for(auto it : delays) { if(rep_counts[idx] > 0 && it.instr_name.find("__" != 0)) - LOG(INFO) << it.instr_name << ";" << rep_counts[idx]; + CPPLOG(INFO) << it.instr_name << ";" << rep_counts[idx]; idx++; } } diff --git a/src/main.cpp b/src/main.cpp index aad92da..9a32241 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -137,11 +137,11 @@ int main(int argc, char* argv[]) { std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as(), &semihosting_cb); } if(!cpu) { - LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; + CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; return 127; } if(!vm) { - LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; + CPPLOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; return 127; } if(clim.count("plugin")) { @@ -177,7 +177,7 @@ int main(int argc, char* argv[]) { } else #endif { - LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl; + CPPLOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl; return 127; } } @@ -215,7 +215,7 @@ int main(int argc, char* argv[]) { auto cycles = clim["instructions"].as(); res = vm->start(cycles, dump); } catch(std::exception& e) { - LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl; + CPPLOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl; res = 2; } // cleanup to let plugins report of needed