fix MISA val
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@ -127,7 +127,7 @@ Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
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XLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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unsigned MISA_VAL = 0b01000000100100000011000100000100;
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unsigned MARCHID_VAL = 0x80000004;
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}
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}
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