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add TGC_D_XRB_NN definition

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Eyck Jentzsch 2021-11-11 12:16:35 +01:00
parent 43d7b99905
commit 7452c5df43
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gen_input/TGC_D_XRB_NN.core_desc Normal file
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import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
InstructionSet X_RB_NN extends RISCVBase {
instructions {
// signed saturate with pre-shift
SSAT {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b000, func7 = <bit position to saturate to>
encoding: sat_bit_pos[6:0] :: rs2[4:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}, {name(sat_bit_pos)}";
behavior: {
signed<XLEN> val_s = (signed<XLEN>)X[rs1];
unsigned<XLEN> pre_shift = (unsigned<XLEN>)X[rs2];
unsigned<XLEN> sat_limit;
signed<XLEN> upper_limit;
signed<XLEN> lower_limit;
if((rd != 0) && (sat_bit_pos > 0) && (sat_bit_pos <= 32) && (pre_shift < 32)) {
sat_limit = (unsigned<XLEN>)(1 << (sat_bit_pos - 1));
upper_limit = (signed)sat_limit - 1;
lower_limit = (signed)sat_limit * (-1);
// important: arithmetical shift right
val_s = val_s >> pre_shift;
X[rd] = (val_s > upper_limit) ? (upper_limit) : ( (val_s < lower_limit) ? (lower_limit) : (val_s) );
}
}
}
// custom packed dot product with accumulation (4x8bit)
PDOT8 {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b001, func7 = 0b0000000
encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b001 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: {
signed<8> op1_0 = (signed<8>)X[rs1][ 7: 0];
signed<8> op1_1 = (signed<8>)X[rs1][15: 8];
signed<8> op1_2 = (signed<8>)X[rs1][23:16];
signed<8> op1_3 = (signed<8>)X[rs1][31:24];
signed<8> op2_0 = (signed<8>)X[rs2][ 7: 0];
signed<8> op2_1 = (signed<8>)X[rs2][15: 8];
signed<8> op2_2 = (signed<8>)X[rs2][23:16];
signed<8> op2_3 = (signed<8>)X[rs2][31:24];
signed<XLEN> op3 = (signed<XLEN>)X[rd];
signed<16> mul0 = op1_0 * op2_0;
signed<16> mul1 = op1_1 * op2_1;
signed<16> mul2 = op1_2 * op2_2;
signed<16> mul3 = op1_3 * op2_3;
signed<19> sum_tmp = mul0 + mul1 + mul2 + mul3;
signed<33> result = op3 + sum_tmp;
if(rd != 0) X[rd] = result[31:0];
}
}
// standard signed multiply accumulate with 32 bit operands and 32 bit result
MAC {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b010, func7 = 0b0000000
encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: {
signed<65> result = (signed)X[rs1] * (signed)X[rs2] + (signed)X[rd];
if(rd != 0) X[rd] = result[31:0];
}
}
// WARNING: The following two HW loop instructions are not fully specified or implemented. The idea is to design the HW loops identical to the RI5CY core (current naming: CV32E40P)
// See "Short Hardware Loop Setup Instructions" from RI5CY specification document from April 2019, revision 4.0: https://www.pulp-platform.org/docs/ri5cy_user_manual.pdf -> page 38, chapter 14.2
// Specific CSRs are introduced to support the HW loops (see page 17, chapter 7).
// lp.setup HW loop (Short Hardware Loop Setup Instruction)
LOOP {
// instruction format: I-type
// opcode space: custom-3 (inst[6:2] = 11110)
// opcode = 0b1111011, func3 = 0b100
// uimmL[11:0] src1 100 0000 L 111 1011 -> lp.setup L,rs1, uimmL
encoding: imm[11:0] :: rs1[4:0] :: 0b100 :: 0b0000 :: L[0:0] :: 0b1111011;
args_disass:"{name(L)}, {name(rs1)}, {imm}";
behavior: {
// L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
/*
lpstart[L] = PC + 4;
lpend[L] = PC + ((unsigned<12>)imm << 1);
lpcount[L] = rs1;
*/
}
}
// lp.setupi HW loop (Short Hardware Loop Setup Instruction with immediate value for loop count)
LOOPI {
// instruction format: I-type
// opcode space: custom-3 (inst[6:2] = 11110)
// opcode = 0b1111011, func3 = 0b101
// uimmL[11:0] uimmS[4:0] 101 0000 L 111 1011 -> lp.setupi L, uimmS, uimmL
encoding: imm2[11:0] :: imm1[4:0] :: 0b101 :: 0b0000 :: L[0:0] :: 0b1111011;
args_disass:"{name(L)}, {imm1}, {imm2}";
behavior: {
// L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
/*
lpstart[L] = PC + 4;
lpend[L] = PC + ((unsigned<5>)imm1 << 1);
lpcount[L] = (unsigned<12>)imm2;
*/
}
}
}
}
Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}