From d31b4ef5a8dd05827ea7724d13c4e70298720230 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Thu, 11 Nov 2021 12:58:57 +0100
Subject: [PATCH] fix MISA val

---
 gen_input/TGC_D_XRB_NN.core_desc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gen_input/TGC_D_XRB_NN.core_desc b/gen_input/TGC_D_XRB_NN.core_desc
index b014856..bec4c2f 100644
--- a/gen_input/TGC_D_XRB_NN.core_desc
+++ b/gen_input/TGC_D_XRB_NN.core_desc
@@ -127,7 +127,7 @@ Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
         XLEN=32;
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MISA_VAL = 0b01000000100100000011000100000100;
         unsigned MARCHID_VAL = 0x80000004;
     }
 }