updates registration of cores for sysc
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@ -48,7 +48,7 @@ else()
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string(TOUPPER ${CORE} CORE)
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list(APPEND LIB_DEFINES CORE_${CORE})
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endforeach()
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message("Defines are ${LIB_DEFINES}")
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message("Core defines are ${LIB_DEFINES}")
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endif()
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if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
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@ -1,12 +1,34 @@
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/*
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* register_tgc_c.cpp
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/*******************************************************************************
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* Copyright (C) 2023 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Created on: Jul 5, 2023
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* Author: eyck
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*/
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <iss/factory.h>
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#include <iss/arch/tgc_c.h>
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@ -17,16 +39,26 @@
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namespace iss {
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namespace {
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volatile std::array<bool, 2> dummy = {
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volatile std::array<bool, 4> dummy = {
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core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
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return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{interp::create(cpu, gdb_port)}};
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}),
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core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
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return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{interp::create(cpu, gdb_port)}};
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}),
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core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{tcc::create(cpu, gdb_port)}};
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}),
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core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{tcc::create(cpu, gdb_port)}};
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})
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};
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}
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