DBT-RISE/DBT-RISE-TGC
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remove mcounteren in M-mode only platform

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This commit is contained in:
Eyck Jentzsch 2021-09-18 11:40:00 +02:00
parent 0fd82f1f3c
commit 65b4db5eca
2 changed files with 4 additions and 4 deletions
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4
incl/iss/arch/riscv_hart_m_p.h
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@ -362,8 +362,8 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid;
csr_rd_cb[mcounteren] = &this_class::read_null;
csr_wr_cb[mcounteren] = &this_class::write_null;
// csr_rd_cb[mcounteren] = &this_class::read_null;
// csr_wr_cb[mcounteren] = &this_class::write_null;
csr_wr_cb[misa] = &this_class::write_null;
csr_wr_cb[mvendorid] = &this_class::write_null;
csr_wr_cb[marchid] = &this_class::write_null;

4
src/vm/interp/vm_tgc_c.cpp
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@ -4138,8 +4138,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
} else {
if (is_jump_to_self_enabled(cond) && (insn == 0x0000006f || (insn&0xffff)==0xa001))
throw simulation_stopped(0); // 'J 0' or 'C.J 0'
if (is_jump_to_self_enabled(cond) &&
(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto f = decode_inst(insn);
pc = (this->*f)(pc, insn);
}