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DBT-RISE-TGC
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optimizes writebacks

This commit is contained in:
Eyck-Alexander Jentzsch 2024-05-08 15:18:38 +02:00
parent ad79a28705
commit 3422c7cd5c
2 changed files with 9 additions and 25 deletions
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10
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -284,11 +284,6 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
cc.cmp(current_trap_state, 0);
cc.jne(jh.trap_entry);
// TODO: Does not need to be done for every instruction, only when needed (by plugin)
cc.comment("//write back regs to mem");
write_reg_to_mem(jh, jh.pc, traits::PC);
write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@ -304,10 +299,7 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
cc.bind(jh.trap_entry);
cc.comment("//Prepare for enter_trap;");
// Make sure cached values are written back
cc.comment("//write back regs to mem");
write_reg_to_mem(jh, jh.pc, traits::PC);
write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
this->write_back(jh);
this->gen_sync(jh, POST_SYNC, -1);
x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);

24
src/vm/asmjit/vm_tgc5c.cpp
View File

@ -2826,12 +2826,12 @@ private:
}
else{
auto res = gen_ext(jh,
(gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
), 64, true);
(gen_operation(jh, imul,
gen_ext(jh,
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true),
gen_ext(jh,
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
), 64, true);
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -4717,11 +4717,6 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
cc.cmp(current_trap_state, 0);
cc.jne(jh.trap_entry);
// TODO: Does not need to be done for every instruction, only when needed (by plugin)
cc.comment("//write back regs to mem");
write_reg_to_mem(jh, jh.pc, traits::PC);
write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@ -4737,10 +4732,7 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
cc.bind(jh.trap_entry);
cc.comment("//Prepare for enter_trap;");
// Make sure cached values are written back
cc.comment("//write back regs to mem");
write_reg_to_mem(jh, jh.pc, traits::PC);
write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
this->write_back(jh);
this->gen_sync(jh, POST_SYNC, -1);
x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
@ -4750,7 +4742,7 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
cc.mov(current_pc, get_ptr_for(jh, traits::PC));
x86::Gp instr = cc.newInt32("instr");
cc.mov(instr, 0); // this is not correct
cc.mov(instr, 0); // FIXME:this is not correct
cc.comment("//enter trap call;");
InvokeNode* call_enter_trap;
cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());