wip checkin
This commit is contained in:
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ad79a28705
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@ -79,21 +79,36 @@ public:
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}
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protected:
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using vm_base<ARCH>::get_reg_ptr;
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using super::get_ptr_for;
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using super::get_reg;
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using super::get_reg_for;
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using super::load_reg_from_mem;
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using super::write_reg_to_mem;
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using super::gen_ext;
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using super::gen_read_mem;
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using super::gen_write_mem;
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using super::gen_wait;
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using super::gen_leave;
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using super::gen_operation;
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using this_class = vm_impl<ARCH>;
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using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
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continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
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void gen_block_prologue(jit_holder& jh) override;
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void gen_block_epilogue(jit_holder& jh) override;
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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void gen_instr_prologue(jit_holder& jh);
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void gen_instr_epilogue(jit_holder& jh);
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inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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#include <vm/asmjit/helper_func.h>
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private:
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/****************************************************************************
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* start opcode definitions
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@ -139,12 +154,14 @@ private:
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}
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x86::Compiler& cc = jh.cc;
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cc.comment(fmt::format("\\n${instr.name}_{:#x}:",pc.val).c_str());
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cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
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this->gen_sync(jh, PRE_SYNC, ${idx});
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pc=pc+ ${instr.length/8};
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gen_instr_prologue(jh, pc.val);
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cc.comment("\\n//behavior:");
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cc.mov(jh.pc, pc.val);
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pc = pc+${instr.length/8};
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cc.mov(jh.next_pc, pc.val);
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gen_instr_prologue(jh);
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cc.comment("//behavior:");
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/*generate behavior*/
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<%instr.behavior.eachLine{%>${it}
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<%}%>
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@ -214,11 +231,6 @@ private:
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
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volatile CODE_WORD x = instr;
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instr = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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template <typename ARCH>
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@ -232,8 +244,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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}
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template <typename ARCH>
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continuation_e
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vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
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continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
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enum {TRAP_ID=1<<16};
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code_word_t instr = 0;
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phys_addr_t paddr(pc);
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@ -251,10 +262,90 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
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f = &this_class::illegal_intruction;
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return (this->*f)(pc, instr, jh);
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
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auto& cc = jh.cc;
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cc.comment("//(*icount)++;");
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cc.inc(get_ptr_for(jh, traits::ICOUNT));
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cc.comment("//*trap_state=*pending_trap;");
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x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
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} // namespace ${coreDef.name.toLowerCase()}
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
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auto& cc = jh.cc;
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cc.comment("//if(*trap_state!=0) goto trap_entry;");
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x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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cc.cmp(current_trap_state, 0);
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cc.jne(jh.trap_entry);
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// TODO: Does not need to be done for every instruction, only when needed (by plugin)
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cc.comment("//write back regs to mem");
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write_reg_to_mem(jh, jh.pc, traits::PC);
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write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
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jh.pc = load_reg_from_mem(jh, traits::PC);
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jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC);
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
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x86::Compiler& cc = jh.cc;
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cc.comment("//return *next_pc;");
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cc.ret(jh.next_pc);
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cc.bind(jh.trap_entry);
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cc.comment("//Prepare for enter_trap;");
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// Make sure cached values are written back
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cc.comment("//write back regs to mem");
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write_reg_to_mem(jh, jh.pc, traits::PC);
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write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
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this->gen_sync(jh, POST_SYNC, -1);
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x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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x86::Gp current_pc = get_reg_for(jh, traits::PC);
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cc.mov(current_pc, get_ptr_for(jh, traits::PC));
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x86::Gp instr = cc.newInt32("instr");
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cc.mov(instr, 0); // this is not correct
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cc.comment("//enter trap call;");
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InvokeNode* call_enter_trap;
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cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
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call_enter_trap->setArg(0, jh.arch_if_ptr);
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call_enter_trap->setArg(1, current_trap_state);
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call_enter_trap->setArg(2, current_pc);
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call_enter_trap->setArg(3, instr);
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x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC);
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cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
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cc.mov(jh.next_pc, current_next_pc);
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cc.comment("//*last_branch = std::numeric_limits<uint32_t>::max();");
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cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits<uint32_t>::max());
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cc.comment("//return *next_pc;");
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cc.ret(jh.next_pc);
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}
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template <typename ARCH>
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inline void vm_impl<ARCH>:: gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
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auto& cc = jh.cc;
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cc.comment("//gen_raise");
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auto tmp1 = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
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cc.mov(get_ptr_for(jh, traits::TRAP_STATE), tmp1);
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cc.mov(jh.next_pc, std::numeric_limits<uint32_t>::max());
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}
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} // namespace tgc5c
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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@ -265,9 +356,9 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
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} // namespace asmjit
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} // namespace iss
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#include <iss/factory.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_mu_p.h>
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#include <iss/factory.h>
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namespace iss {
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namespace {
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volatile std::array<bool, 2> dummy = {
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@ -75,7 +75,7 @@ int main(int argc, char* argv[]) {
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("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
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("mem,m", po::value<std::string>(), "the memory input file")
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("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
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("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, tcc")
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("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, llvm, tcc, asmjit")
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("isa", po::value<std::string>()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list");
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// clang-format on
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auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
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@ -1,539 +0,0 @@
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#include <asmjit/asmjit.h>
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#include <iss/asmjit/jit_helper.h>
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x86::Mem get_reg_ptr(jit_holder& jh, unsigned idx) {
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x86::Gp tmp_ptr = jh.cc.newUIntPtr("tmp_ptr");
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jh.cc.mov(tmp_ptr, jh.regs_base_ptr);
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jh.cc.add(tmp_ptr, traits::reg_byte_offsets[idx]);
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switch(traits::reg_bit_widths[idx]) {
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case 8:
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return x86::ptr_8(tmp_ptr);
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case 16:
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return x86::ptr_16(tmp_ptr);
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case 32:
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return x86::ptr_32(tmp_ptr);
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case 64:
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return x86::ptr_64(tmp_ptr);
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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}
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x86::Gp get_reg_for(jit_holder& jh, unsigned idx) {
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// TODO can check for regs in jh and return them instead of creating new ones
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switch(traits::reg_bit_widths[idx]) {
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case 8:
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return jh.cc.newInt8();
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case 16:
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return jh.cc.newInt16();
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case 32:
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return jh.cc.newInt32();
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case 64:
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return jh.cc.newInt64();
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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}
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x86::Gp get_reg_for(jit_holder& jh, unsigned size, bool is_signed) {
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if(is_signed)
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switch(size) {
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case 8:
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return jh.cc.newInt8();
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case 16:
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return jh.cc.newInt16();
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case 32:
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return jh.cc.newInt32();
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case 64:
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return jh.cc.newInt64();
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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else
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switch(size) {
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case 8:
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return jh.cc.newUInt8();
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case 16:
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return jh.cc.newUInt16();
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case 32:
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return jh.cc.newUInt32();
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case 64:
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return jh.cc.newUInt64();
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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}
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inline x86::Gp load_reg_from_mem(jit_holder& jh, unsigned idx) {
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auto ptr = get_reg_ptr(jh, idx);
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auto reg = get_reg_for(jh, idx);
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jh.cc.mov(reg, ptr);
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return reg;
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}
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inline void write_reg_to_mem(jit_holder& jh, x86::Gp reg, unsigned idx) {
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auto ptr = get_reg_ptr(jh, idx);
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jh.cc.mov(ptr, reg);
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}
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void gen_instr_prologue(jit_holder& jh, addr_t pc) {
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auto& cc = jh.cc;
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cc.mov(jh.pc, pc);
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cc.comment("\n//(*icount)++;");
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cc.inc(get_reg_ptr(jh, traits::ICOUNT));
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cc.comment("\n//*pc=*next_pc;");
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cc.mov(get_reg_ptr(jh, traits::PC), jh.next_pc);
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cc.comment("\n//*trap_state=*pending_trap;");
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x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
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cc.mov(get_reg_ptr(jh, traits::PENDING_TRAP), current_trap_state);
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cc.comment("\n//increment *next_pc");
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cc.mov(jh.next_pc, pc);
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}
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void gen_instr_epilogue(jit_holder& jh) {
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auto& cc = jh.cc;
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cc.comment("\n//if(*trap_state!=0) goto trap_entry;");
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x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
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cc.cmp(current_trap_state, 0);
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cc.jne(jh.trap_entry);
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// TODO: Does not need to be done for every instruction, only when needed
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cc.comment("\n//write back regs to mem");
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write_reg_to_mem(jh, jh.pc, traits::PC);
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write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
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}
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void gen_block_prologue(jit_holder& jh) override {
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jh.pc = load_reg_from_mem(jh, traits::PC);
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jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC);
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}
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void gen_block_epilogue(jit_holder& jh) override {
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x86::Compiler& cc = jh.cc;
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cc.comment("\n//return *next_pc;");
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cc.ret(jh.next_pc);
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cc.bind(jh.trap_entry);
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cc.comment("\n//Prepare for enter_trap;");
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// Make sure cached values are written back
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cc.comment("\n//write back regs to mem");
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write_reg_to_mem(jh, jh.pc, traits::PC);
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write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
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this->gen_sync(jh, POST_SYNC, -1);
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x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
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x86::Gp current_pc = get_reg_for(jh, traits::PC);
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cc.mov(current_pc, get_reg_ptr(jh, traits::PC));
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x86::Gp instr = cc.newInt32("instr");
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cc.mov(instr, 0); // this is not correct
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cc.comment("\n//enter trap call;");
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InvokeNode* call_enter_trap;
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cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
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call_enter_trap->setArg(0, jh.arch_if_ptr);
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call_enter_trap->setArg(1, current_trap_state);
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call_enter_trap->setArg(2, current_pc);
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call_enter_trap->setArg(3, instr);
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x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC);
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cc.mov(current_next_pc, get_reg_ptr(jh, traits::NEXT_PC));
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cc.mov(jh.next_pc, current_next_pc);
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cc.comment("\n//*last_branch = std::numeric_limits<uint32_t>::max();");
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cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), std::numeric_limits<uint32_t>::max());
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cc.comment("\n//return *next_pc;");
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cc.ret(jh.next_pc);
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}
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/*
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->core.reg.trap_state = trap_val;
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this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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}
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*/
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inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
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auto& cc = jh.cc;
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cc.comment("//gen_raise");
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auto tmp1 = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
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cc.mov(get_reg_ptr(jh, traits::TRAP_STATE), tmp1);
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auto tmp2 = get_reg_for(jh, traits::NEXT_PC);
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cc.mov(tmp2, std::numeric_limits<uint32_t>::max());
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cc.mov(get_reg_ptr(jh, traits::NEXT_PC), tmp2);
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}
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inline void gen_wait(jit_holder& jh, unsigned type) { jh.cc.comment("//gen_wait"); }
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inline void gen_leave(jit_holder& jh, unsigned lvl) { jh.cc.comment("//gen_leave"); }
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enum operation { add, sub, band, bor, bxor, shl, sar, shr };
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template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
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x86::Gp gen_operation(jit_holder& jh, operation op, x86::Gp a, T b) {
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x86::Compiler& cc = jh.cc;
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switch(op) {
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case add: {
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cc.add(a, b);
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break;
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}
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case sub: {
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cc.sub(a, b);
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break;
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}
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case band: {
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cc.and_(a, b);
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break;
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}
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||||
case bor: {
|
||||
cc.or_(a, b);
|
||||
break;
|
||||
}
|
||||
case bxor: {
|
||||
cc.xor_(a, b);
|
||||
break;
|
||||
}
|
||||
case shl: {
|
||||
cc.shl(a, b);
|
||||
break;
|
||||
}
|
||||
case sar: {
|
||||
cc.sar(a, b);
|
||||
break;
|
||||
}
|
||||
case shr: {
|
||||
cc.shr(a, b);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (operation)", op));
|
||||
}
|
||||
return a;
|
||||
}
|
||||
|
||||
enum three_operand_operation { imul, mul, idiv, div, srem, urem };
|
||||
|
||||
x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, x86::Gp b) {
|
||||
x86::Compiler& cc = jh.cc;
|
||||
switch(op) {
|
||||
case imul: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.imul(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case mul: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.mul(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case idiv: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.mov(dummy, 0);
|
||||
cc.idiv(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case div: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.mov(dummy, 0);
|
||||
cc.div(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case srem: {
|
||||
x86::Gp rem = cc.newInt32();
|
||||
cc.mov(rem, 0);
|
||||
auto a_reg = cc.newInt32();
|
||||
cc.mov(a_reg, a.r32());
|
||||
cc.idiv(rem, a_reg, b.r32());
|
||||
return rem;
|
||||
}
|
||||
case urem: {
|
||||
x86::Gp rem = cc.newInt32();
|
||||
cc.mov(rem, 0);
|
||||
auto a_reg = cc.newInt32();
|
||||
cc.mov(a_reg, a.r32());
|
||||
cc.div(rem, a_reg, b.r32());
|
||||
return rem;
|
||||
}
|
||||
|
||||
default:
|
||||
throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (three_operand)", op));
|
||||
}
|
||||
return a;
|
||||
}
|
||||
template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
|
||||
x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, T b) {
|
||||
x86::Gp b_reg = jh.cc.newInt32();
|
||||
/* switch(a.size()){
|
||||
case 1: b_reg = jh.cc.newInt8(); break;
|
||||
case 2: b_reg = jh.cc.newInt16(); break;
|
||||
case 4: b_reg = jh.cc.newInt32(); break;
|
||||
case 8: b_reg = jh.cc.newInt64(); break;
|
||||
default: throw std::runtime_error(fmt::format("Invalid size ({}) in gen operation", a.size()));
|
||||
} */
|
||||
jh.cc.mov(b_reg, b);
|
||||
return gen_operation(jh, op, a, b_reg);
|
||||
}
|
||||
enum comparison_operation { land, lor, eq, ne, lt, ltu, gt, gtu, lte, lteu, gte, gteu };
|
||||
|
||||
template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
|
||||
x86::Gp gen_operation(jit_holder& jh, comparison_operation op, x86::Gp a, T b) {
|
||||
x86::Compiler& cc = jh.cc;
|
||||
x86::Gp tmp = cc.newInt8();
|
||||
cc.mov(tmp, 1);
|
||||
Label label_then = cc.newLabel();
|
||||
cc.cmp(a, b);
|
||||
switch(op) {
|
||||
case eq:
|
||||
cc.je(label_then);
|
||||
break;
|
||||
case ne:
|
||||
cc.jne(label_then);
|
||||
break;
|
||||
case lt:
|
||||
cc.jl(label_then);
|
||||
break;
|
||||
case ltu:
|
||||
cc.jb(label_then);
|
||||
break;
|
||||
case gt:
|
||||
cc.jg(label_then);
|
||||
break;
|
||||
case gtu:
|
||||
cc.ja(label_then);
|
||||
break;
|
||||
case lte:
|
||||
cc.jle(label_then);
|
||||
break;
|
||||
case lteu:
|
||||
cc.jbe(label_then);
|
||||
break;
|
||||
case gte:
|
||||
cc.jge(label_then);
|
||||
break;
|
||||
case gteu:
|
||||
cc.jae(label_then);
|
||||
break;
|
||||
case land: {
|
||||
Label label_false = cc.newLabel();
|
||||
cc.cmp(a, 0);
|
||||
cc.je(label_false);
|
||||
auto b_reg = cc.newInt8();
|
||||
cc.mov(b_reg, b);
|
||||
cc.cmp(b_reg, 0);
|
||||
cc.je(label_false);
|
||||
cc.jmp(label_then);
|
||||
cc.bind(label_false);
|
||||
break;
|
||||
}
|
||||
case lor: {
|
||||
cc.cmp(a, 0);
|
||||
cc.jne(label_then);
|
||||
auto b_reg = cc.newInt8();
|
||||
cc.mov(b_reg, b);
|
||||
cc.cmp(b_reg, 0);
|
||||
cc.jne(label_then);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (comparison)", op));
|
||||
}
|
||||
cc.mov(tmp, 0);
|
||||
cc.bind(label_then);
|
||||
return tmp;
|
||||
}
|
||||
enum binary_operation { lnot, inc, dec, bnot, neg };
|
||||
|
||||
x86::Gp gen_operation(jit_holder& jh, binary_operation op, x86::Gp a) {
|
||||
x86::Compiler& cc = jh.cc;
|
||||
switch(op) {
|
||||
case lnot:
|
||||
throw std::runtime_error("Current operation not supported in gen_operation(lnot)");
|
||||
case inc: {
|
||||
cc.inc(a);
|
||||
break;
|
||||
}
|
||||
case dec: {
|
||||
cc.dec(a);
|
||||
break;
|
||||
}
|
||||
case bnot: {
|
||||
cc.not_(a);
|
||||
break;
|
||||
}
|
||||
case neg: {
|
||||
cc.neg(a);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (unary)", op));
|
||||
}
|
||||
return a;
|
||||
}
|
||||
|
||||
template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
|
||||
inline x86::Gp gen_ext(jit_holder& jh, T val, unsigned size, bool is_signed) {
|
||||
auto val_reg = get_reg_for(jh, sizeof(val) * 8, is_signed);
|
||||
jh.cc.mov(val_reg, val);
|
||||
return gen_ext(jh, val_reg, size, is_signed);
|
||||
}
|
||||
inline x86::Gp gen_ext(jit_holder& jh, x86::Gp val, unsigned size, bool is_signed) {
|
||||
auto& cc = jh.cc;
|
||||
if(is_signed) {
|
||||
switch(val.size()) {
|
||||
case 1:
|
||||
cc.cbw(val);
|
||||
break;
|
||||
case 2:
|
||||
cc.cwde(val);
|
||||
break;
|
||||
case 4:
|
||||
cc.cdqe(val);
|
||||
break;
|
||||
case 8:
|
||||
break;
|
||||
default:
|
||||
throw std::runtime_error("Invalid register size in gen_ext");
|
||||
}
|
||||
}
|
||||
switch(size) {
|
||||
case 8:
|
||||
cc.and_(val, std::numeric_limits<uint8_t>::max());
|
||||
return val.r8();
|
||||
case 16:
|
||||
cc.and_(val, std::numeric_limits<uint16_t>::max());
|
||||
return val.r16();
|
||||
case 32:
|
||||
cc.and_(val, std::numeric_limits<uint32_t>::max());
|
||||
return val.r32();
|
||||
case 64:
|
||||
cc.and_(val, std::numeric_limits<uint64_t>::max());
|
||||
return val.r64();
|
||||
case 128:
|
||||
return val.r64();
|
||||
default:
|
||||
throw std::runtime_error("Invalid size in gen_ext");
|
||||
}
|
||||
}
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, uint32_t length) {
|
||||
x86::Compiler& cc = jh.cc;
|
||||
auto ret_reg = cc.newInt32();
|
||||
|
||||
auto mem_type_reg = cc.newInt32();
|
||||
cc.mov(mem_type_reg, type);
|
||||
|
||||
auto space_reg = cc.newInt32();
|
||||
cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
|
||||
|
||||
auto val_ptr = cc.newUIntPtr();
|
||||
cc.mov(val_ptr, read_mem_buf);
|
||||
|
||||
InvokeNode* invokeNode;
|
||||
uint64_t mask = 0;
|
||||
x86::Gp val_reg = cc.newInt64();
|
||||
|
||||
switch(length) {
|
||||
case 1: {
|
||||
cc.invoke(&invokeNode, &read_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint8_t>::max();
|
||||
break;
|
||||
}
|
||||
case 2: {
|
||||
cc.invoke(&invokeNode, &read_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint16_t>::max();
|
||||
break;
|
||||
}
|
||||
case 4: {
|
||||
cc.invoke(&invokeNode, &read_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint32_t>::max();
|
||||
break;
|
||||
}
|
||||
case 8: {
|
||||
cc.invoke(&invokeNode, &read_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint64_t>::max();
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw std::runtime_error(fmt::format("Invalid length ({}) in gen_read_mem", length));
|
||||
}
|
||||
|
||||
invokeNode->setRet(0, ret_reg);
|
||||
invokeNode->setArg(0, jh.arch_if_ptr);
|
||||
invokeNode->setArg(1, space_reg);
|
||||
invokeNode->setArg(2, mem_type_reg);
|
||||
invokeNode->setArg(3, addr);
|
||||
invokeNode->setArg(4, val_ptr);
|
||||
cc.cmp(ret_reg, 0);
|
||||
cc.jne(jh.trap_entry);
|
||||
|
||||
cc.mov(val_reg, x86::ptr_64(val_ptr));
|
||||
cc.and_(val_reg, mask);
|
||||
return val_reg;
|
||||
}
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp length) {
|
||||
throw std::runtime_error("Invalid gen_read_mem");
|
||||
}
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp length) {
|
||||
throw std::runtime_error("Invalid gen_read_mem");
|
||||
}
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, uint32_t length) {
|
||||
auto addr_reg = jh.cc.newInt64();
|
||||
jh.cc.mov(addr_reg, addr);
|
||||
|
||||
return gen_read_mem(jh, type, addr_reg, length);
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, int64_t val, uint32_t length) {
|
||||
auto val_reg = get_reg_for(jh, length * 8, true);
|
||||
jh.cc.mov(val_reg, val);
|
||||
gen_write_mem(jh, type, addr, val_reg, length);
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp val, uint32_t length) {
|
||||
x86::Compiler& cc = jh.cc;
|
||||
assert(val.size() == length);
|
||||
auto mem_type_reg = cc.newInt32();
|
||||
jh.cc.mov(mem_type_reg, type);
|
||||
auto space_reg = cc.newInt32();
|
||||
jh.cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
|
||||
auto ret_reg = cc.newInt32();
|
||||
InvokeNode* invokeNode;
|
||||
switch(length) {
|
||||
case 1:
|
||||
cc.invoke(&invokeNode, &write_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint8_t>());
|
||||
|
||||
break;
|
||||
case 2:
|
||||
cc.invoke(&invokeNode, &write_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint16_t>());
|
||||
break;
|
||||
case 4:
|
||||
cc.invoke(&invokeNode, &write_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint32_t>());
|
||||
break;
|
||||
case 8:
|
||||
cc.invoke(&invokeNode, &write_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint64_t>());
|
||||
|
||||
break;
|
||||
default:
|
||||
throw std::runtime_error("Invalid register size in gen_ext");
|
||||
}
|
||||
invokeNode->setRet(0, ret_reg);
|
||||
invokeNode->setArg(0, jh.arch_if_ptr);
|
||||
invokeNode->setArg(1, space_reg);
|
||||
invokeNode->setArg(2, mem_type_reg);
|
||||
invokeNode->setArg(3, addr);
|
||||
invokeNode->setArg(4, val);
|
||||
|
||||
cc.cmp(ret_reg, 0);
|
||||
cc.jne(jh.trap_entry);
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp val, uint32_t length) {
|
||||
auto addr_reg = jh.cc.newUInt64();
|
||||
jh.cc.mov(addr_reg, addr);
|
||||
gen_write_mem(jh, type, addr_reg, val, length);
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, int64_t val, uint32_t length) {
|
||||
auto val_reg = get_reg_for(jh, length * 8, true);
|
||||
jh.cc.mov(val_reg, val);
|
||||
|
||||
auto addr_reg = jh.cc.newUInt64();
|
||||
jh.cc.mov(addr_reg, addr);
|
||||
gen_write_mem(jh, type, addr_reg, val_reg, length);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue