fix exception behavior
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ac6d7ea5d4
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039746112b
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@ -959,9 +959,16 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
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if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
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// store ret addr in xepc register
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csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
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/*
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* write mtval if new_priv=M_MODE, spec says:
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* When a hardware breakpoint is triggered, or an instruction-fetch, load,
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* or store address-misaligned,
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* access, or page-fault exception occurs, mtval is written with the
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* faulting effective address.
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*/
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switch(cause){
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case 0:
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csr[mtval] = addr;
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csr[mtval] = static_cast<reg_t>(addr);
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break;
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case 2:
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csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
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@ -970,10 +977,14 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
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//TODO: implement debug mode behavior
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// csr[dpc] = addr;
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// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
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csr[mtval] = addr;
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csr[mtval] = 0;
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break;
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case 4:
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case 6:
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csr[mtval] = fault_data;
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break;
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default:
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csr[mtval] = fault_data;
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csr[mtval] = 0;
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}
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fault_data = 0;
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} else {
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@ -1220,7 +1220,26 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
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* access, or page-fault exception occurs, mtval is written with the
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* faulting effective address.
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*/
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csr[utval | (new_priv << 8)] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
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switch(cause){
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case 0:
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csr[utval | (new_priv << 8)] = static_cast<reg_t>(addr);
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break;
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case 2:
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csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
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break;
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case 3:
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//TODO: implement debug mode behavior
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// csr[dpc] = addr;
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// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
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csr[utval | (new_priv << 8)] = 0;
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break;
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case 4:
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case 6:
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csr[utval | (new_priv << 8)] = fault_data;
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break;
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default:
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csr[utval | (new_priv << 8)] = 0;
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}
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fault_data = 0;
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} else {
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if (this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
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