add debug feature to platform
This commit is contained in:
parent
a89f00da19
commit
ac6d7ea5d4
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@ -43,6 +43,8 @@ namespace arch {
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enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
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enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8};
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enum riscv_csr {
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/* user-level CSR */
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// User Trap Setup
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@ -164,7 +166,8 @@ enum riscv_csr {
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// Debug Mode Registers
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dcsr = 0x7B0,
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dpc = 0x7B1,
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dscratch = 0x7B2
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dscratch0 = 0x7B2,
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dscratch1 = 0x7B3
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};
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@ -66,7 +66,7 @@
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namespace iss {
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namespace arch {
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template <typename BASE> class riscv_hart_m_p : public BASE {
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template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_m_p : public BASE {
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protected:
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const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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const std::array<const char *, 16> trap_str = {{""
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@ -92,7 +92,7 @@ protected:
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"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
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public:
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using core = BASE;
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using this_class = riscv_hart_m_p<BASE>;
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using this_class = riscv_hart_m_p<BASE, FEAT>;
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using phys_addr_t = typename core::phys_addr_t;
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using reg_t = typename core::reg_t;
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using addr_t = typename core::addr_t;
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@ -221,7 +221,7 @@ public:
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protected:
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struct riscv_instrumentation_if : public iss::instrumentation_if {
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riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
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riscv_instrumentation_if(riscv_hart_m_p<BASE, FEAT> &arch)
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: arch(arch) {}
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/**
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* get the name of this architecture
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@ -236,7 +236,7 @@ protected:
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virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
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riscv_hart_m_p<BASE> &arch;
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riscv_hart_m_p<BASE, FEAT> &arch;
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};
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friend struct riscv_instrumentation_if;
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@ -246,6 +246,9 @@ protected:
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virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
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virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
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iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data);
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iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data);
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virtual iss::status read_csr(unsigned addr, reg_t &val);
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virtual iss::status write_csr(unsigned addr, reg_t val);
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@ -270,10 +273,23 @@ protected:
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std::unordered_map<uint64_t, uint8_t> atomic_reservation;
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std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
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std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
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uint8_t clic_cfg_reg{0};
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uint32_t clic_info_reg{0};
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std::array<uint32_t, 32> clic_inttrig_reg;
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union clic_int_reg_t {
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struct{
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uint8_t ip;
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uint8_t ie;
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uint8_t attr;
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uint8_t ctl;
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};
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uint32_t raw;
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};
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std::vector<clic_int_reg_t> clic_int_reg;
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private:
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iss::status read_reg(unsigned addr, reg_t &val);
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iss::status write_reg(unsigned addr, reg_t val);
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iss::status read_csr_reg(unsigned addr, reg_t &val);
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iss::status write_csr_reg(unsigned addr, reg_t val);
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iss::status read_null(unsigned addr, reg_t &val);
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iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
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iss::status read_cycle(unsigned addr, reg_t &val);
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@ -291,17 +307,22 @@ private:
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iss::status write_ip(unsigned addr, reg_t val);
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iss::status read_hartid(unsigned addr, reg_t &val);
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status write_dcsr(unsigned addr, reg_t val);
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reg_t mhartid_reg{0x0};
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std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
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std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
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protected:
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void check_interrupt();
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bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
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uint64_t clic_base_addr{0};
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unsigned clic_num_irq{0};
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unsigned clic_num_trigger{0};
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unsigned mcause_max_irq{16};
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};
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template <typename BASE>
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riscv_hart_m_p<BASE>::riscv_hart_m_p()
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template <typename BASE, features_e FEAT>
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riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
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: state()
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, instr_if(*this) {
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// reset values
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@ -309,32 +330,33 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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csr[mvendorid] = 0x669;
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csr[marchid] = traits<BASE>::MARCHID_VAL;
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csr[mimpid] = 1;
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csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
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uart_buf.str("");
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for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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csr_wr_cb[addr] = &this_class::write_reg;
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csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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csr_wr_cb[addr] = &this_class::write_reg;
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csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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csr_wr_cb[addr] = &this_class::write_reg;
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csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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}
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for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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//csr_wr_cb[addr] = &this_class::write_reg;
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//csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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// common regs
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const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
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for(auto addr: addrs) {
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csr_rd_cb[addr] = &this_class::read_reg;
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csr_wr_cb[addr] = &this_class::write_reg;
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csr_rd_cb[addr] = &this_class::read_csr_reg;
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csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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// special handling & overrides
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csr_rd_cb[time] = &this_class::read_time;
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@ -362,15 +384,23 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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csr_rd_cb[mie] = &this_class::read_ie;
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csr_wr_cb[mie] = &this_class::write_ie;
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csr_rd_cb[mhartid] = &this_class::read_hartid;
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// csr_rd_cb[mcounteren] = &this_class::read_null;
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// csr_wr_cb[mcounteren] = &this_class::write_null;
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csr_wr_cb[misa] = &this_class::write_null;
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csr_wr_cb[mvendorid] = &this_class::write_null;
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csr_wr_cb[marchid] = &this_class::write_null;
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csr_wr_cb[mimpid] = &this_class::write_null;
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if(FEAT & FEAT_DEBUG){
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csr_wr_cb[dscratch0] = &this_class::write_csr_reg;
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csr_rd_cb[dscratch0] = &this_class::read_csr_reg;
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csr_wr_cb[dscratch1] = &this_class::write_csr_reg;
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csr_rd_cb[dscratch1] = &this_class::read_csr_reg;
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csr_wr_cb[dpc] = &this_class::write_csr_reg;
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csr_rd_cb[dpc] = &this_class::read_csr_reg;
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csr_wr_cb[dcsr] = &this_class::write_dcsr;
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csr_rd_cb[dcsr] = &this_class::read_csr_reg;
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}
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}
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template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
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template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
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FILE *fp = fopen(name.c_str(), "r");
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if (fp) {
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std::array<char, 5> buf;
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@ -436,8 +466,8 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
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throw std::runtime_error("memory load file not found");
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}
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template <typename BASE>
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iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, uint8_t *const data) {
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#ifndef NDEBUG
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if (access && iss::access_type::DEBUG) {
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@ -505,8 +535,8 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
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}
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}
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template <typename BASE>
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iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, const uint8_t *const data) {
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#ifndef NDEBUG
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const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
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@ -621,7 +651,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
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}
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr(unsigned addr, reg_t &val) {
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if (addr >= csr.size()) return iss::Err;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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if (this->reg.PRIV < req_priv_lvl) // not having required privileges
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@ -632,7 +662,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned add
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return (this->*(it->second))(addr, val);
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr(unsigned addr, reg_t val) {
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if (addr >= csr.size()) return iss::Err;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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if (this->reg.PRIV < req_priv_lvl) // not having required privileges
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@ -645,22 +675,22 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned ad
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return (this->*(it->second))(addr, val);
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr_reg(unsigned addr, reg_t &val) {
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val = csr[addr];
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_null(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_null(unsigned addr, reg_t &val) {
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val = 0;
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr_reg(unsigned addr, reg_t val) {
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csr[addr] = val;
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
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auto cycle_val = this->reg.icount + cycle_offset;
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if (addr == mcycle) {
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val = static_cast<reg_t>(cycle_val);
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@ -671,7 +701,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned a
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
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if (sizeof(typename traits<BASE>::reg_t) != 4) {
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if (addr == mcycleh)
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return iss::Err;
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@ -687,7 +717,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
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if ((addr&0xff) == (minstret&0xff)) {
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val = static_cast<reg_t>(this->reg.instret);
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} else if ((addr&0xff) == (minstreth&0xff)) {
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@ -697,7 +727,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
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if (sizeof(typename traits<BASE>::reg_t) != 4) {
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if ((addr&0xff) == (minstreth&0xff))
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return iss::Err;
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@ -713,7 +743,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigne
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
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uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
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if (addr == time) {
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val = static_cast<reg_t>(time_val);
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@ -724,50 +754,50 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
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val = csr[mtvec] & ~2;
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
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val = state.mstatus & hart_state_type::get_mask();
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
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state.write_mstatus(val);
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check_interrupt();
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cause(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
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csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
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val = csr[mie];
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_hartid(unsigned addr, reg_t &val) {
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val = mhartid_reg;
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
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auto mask = get_irq_mask();
|
||||
csr[mie] = (csr[mie] & ~mask) | (val & mask);
|
||||
check_interrupt();
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
|
||||
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
|
||||
val = csr[mip];
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
|
||||
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
|
||||
auto mask = get_irq_mask();
|
||||
mask &= ~(1 << 7); // MTIP is read only
|
||||
csr[mip] = (csr[mip] & ~mask) | (val & mask);
|
||||
|
|
@ -775,13 +805,22 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned add
|
|||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) {
|
||||
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
|
||||
csr[addr] = val & get_pc_mask();
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE>
|
||||
iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
|
||||
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr(unsigned addr, reg_t val) {
|
||||
// +-------------- ebreakm
|
||||
// | +---------- stepi
|
||||
// | | +++----- cause
|
||||
// | | ||| +- step
|
||||
csr[addr] = val & 0b1000100111000100U;
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE, features_e FEAT>
|
||||
iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
|
||||
if(mem_read_cb) return mem_read_cb(paddr, length, data);
|
||||
switch (paddr.val) {
|
||||
case 0x0200BFF8: { // CLINT base, mtime reg
|
||||
|
|
@ -805,8 +844,8 @@ iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, u
|
|||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE>
|
||||
iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
|
||||
template <typename BASE, features_e FEAT>
|
||||
iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
|
||||
if(mem_write_cb) return mem_write_cb(paddr, length, data);
|
||||
switch (paddr.val) {
|
||||
case 0x10013000: // UART0 base, TXFIFO reg
|
||||
|
|
@ -883,12 +922,12 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
|
|||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
|
||||
template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>::reset(uint64_t address) {
|
||||
BASE::reset(address);
|
||||
state.mstatus = hart_state_type::mstatus_reset_val;
|
||||
}
|
||||
|
||||
template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
|
||||
template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
|
||||
//auto ideleg = csr[mideleg];
|
||||
// Multiple simultaneous interrupts and traps at the same privilege level are
|
||||
// handled in the following decreasing priority order:
|
||||
|
|
@ -910,14 +949,14 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
|
|||
}
|
||||
}
|
||||
|
||||
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
|
||||
template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
|
||||
// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
|
||||
// calculate and write mcause val
|
||||
auto trap_id = bit_sub<0, 16>(flags);
|
||||
auto cause = bit_sub<16, 15>(flags);
|
||||
if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
|
||||
// calculate effective privilege level
|
||||
if (trap_id == 0) { // exception
|
||||
if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
|
||||
// store ret addr in xepc register
|
||||
csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
|
||||
switch(cause){
|
||||
|
|
@ -927,6 +966,12 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
|
|||
case 2:
|
||||
csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
|
||||
break;
|
||||
case 3:
|
||||
//TODO: implement debug mode behavior
|
||||
// csr[dpc] = addr;
|
||||
// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
|
||||
csr[mtval] = addr;
|
||||
break;
|
||||
default:
|
||||
csr[mtval] = fault_data;
|
||||
}
|
||||
|
|
@ -969,7 +1014,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
|
|||
return this->reg.NEXT_PC;
|
||||
}
|
||||
|
||||
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
|
||||
template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::leave_trap(uint64_t flags) {
|
||||
state.mstatus.MIE = state.mstatus.MPIE;
|
||||
state.mstatus.MPIE = 1;
|
||||
// sets the pc to the value stored in the x epc register.
|
||||
|
|
|
|||
|
|
@ -66,8 +66,6 @@
|
|||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N, FEAT_CLIC};
|
||||
|
||||
template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE {
|
||||
protected:
|
||||
const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
|
||||
|
|
@ -326,6 +324,7 @@ private:
|
|||
iss::status write_edeleg(unsigned addr, reg_t val);
|
||||
iss::status read_hartid(unsigned addr, reg_t &val);
|
||||
iss::status write_epc(unsigned addr, reg_t val);
|
||||
iss::status write_dcsr(unsigned addr, reg_t val);
|
||||
iss::status write_intstatus(unsigned addr, reg_t val);
|
||||
iss::status write_intthresh(unsigned addr, reg_t val);
|
||||
|
||||
|
|
@ -464,6 +463,16 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
|
|||
clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
|
||||
mcause_max_irq=clic_num_irq+16;
|
||||
}
|
||||
if(FEAT & FEAT_DEBUG){
|
||||
csr_wr_cb[dscratch0] = &this_class::write_csr_reg;
|
||||
csr_rd_cb[dscratch0] = &this_class::read_csr_reg;
|
||||
csr_wr_cb[dscratch1] = &this_class::write_csr_reg;
|
||||
csr_rd_cb[dscratch1] = &this_class::read_csr_reg;
|
||||
csr_wr_cb[dpc] = &this_class::write_csr_reg;
|
||||
csr_rd_cb[dpc] = &this_class::read_csr_reg;
|
||||
csr_wr_cb[dcsr] = &this_class::write_dcsr;
|
||||
csr_rd_cb[dcsr] = &this_class::read_csr_reg;
|
||||
}
|
||||
}
|
||||
|
||||
template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {
|
||||
|
|
@ -968,6 +977,14 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
|
|||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr(unsigned addr, reg_t val) {
|
||||
// +-------------- ebreakm
|
||||
// | +---------- stepi
|
||||
// | | +++----- cause
|
||||
// | | ||| +- step
|
||||
csr[addr] = val & 0b1000100111000100U;
|
||||
return iss::Ok;
|
||||
}
|
||||
template<typename BASE, features_e FEAT>
|
||||
iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
|
||||
csr[addr]= val &0xff;
|
||||
|
|
|
|||
Loading…
Reference in New Issue