diff --git a/incl/iss/arch/riscv_hart_common.h b/incl/iss/arch/riscv_hart_common.h index 7cd6f72..ffe87bc 100644 --- a/incl/iss/arch/riscv_hart_common.h +++ b/incl/iss/arch/riscv_hart_common.h @@ -43,6 +43,8 @@ namespace arch { enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 }; +enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8}; + enum riscv_csr { /* user-level CSR */ // User Trap Setup @@ -164,7 +166,8 @@ enum riscv_csr { // Debug Mode Registers dcsr = 0x7B0, dpc = 0x7B1, - dscratch = 0x7B2 + dscratch0 = 0x7B2, + dscratch1 = 0x7B3 }; diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h index b76f14d..fa7324a 100644 --- a/incl/iss/arch/riscv_hart_m_p.h +++ b/incl/iss/arch/riscv_hart_m_p.h @@ -66,7 +66,7 @@ namespace iss { namespace arch { -template class riscv_hart_m_p : public BASE { +template class riscv_hart_m_p : public BASE { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; const std::array trap_str = {{"" @@ -92,7 +92,7 @@ protected: "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; public: using core = BASE; - using this_class = riscv_hart_m_p; + using this_class = riscv_hart_m_p; using phys_addr_t = typename core::phys_addr_t; using reg_t = typename core::reg_t; using addr_t = typename core::addr_t; @@ -221,7 +221,7 @@ public: protected: struct riscv_instrumentation_if : public iss::instrumentation_if { - riscv_instrumentation_if(riscv_hart_m_p &arch) + riscv_instrumentation_if(riscv_hart_m_p &arch) : arch(arch) {} /** * get the name of this architecture @@ -236,7 +236,7 @@ protected: virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; }; - riscv_hart_m_p &arch; + riscv_hart_m_p &arch; }; friend struct riscv_instrumentation_if; @@ -246,6 +246,9 @@ protected: virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data); virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data); + iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data); + iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data); + virtual iss::status read_csr(unsigned addr, reg_t &val); virtual iss::status write_csr(unsigned addr, reg_t val); @@ -270,10 +273,23 @@ protected: std::unordered_map atomic_reservation; std::unordered_map csr_rd_cb; std::unordered_map csr_wr_cb; + uint8_t clic_cfg_reg{0}; + uint32_t clic_info_reg{0}; + std::array clic_inttrig_reg; + union clic_int_reg_t { + struct{ + uint8_t ip; + uint8_t ie; + uint8_t attr; + uint8_t ctl; + }; + uint32_t raw; + }; + std::vector clic_int_reg; private: - iss::status read_reg(unsigned addr, reg_t &val); - iss::status write_reg(unsigned addr, reg_t val); + iss::status read_csr_reg(unsigned addr, reg_t &val); + iss::status write_csr_reg(unsigned addr, reg_t val); iss::status read_null(unsigned addr, reg_t &val); iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;} iss::status read_cycle(unsigned addr, reg_t &val); @@ -291,17 +307,22 @@ private: iss::status write_ip(unsigned addr, reg_t val); iss::status read_hartid(unsigned addr, reg_t &val); iss::status write_epc(unsigned addr, reg_t val); - + iss::status write_dcsr(unsigned addr, reg_t val); reg_t mhartid_reg{0x0}; std::functionmem_read_cb; std::function mem_write_cb; protected: void check_interrupt(); + bool pmp_check(const access_type type, const uint64_t addr, const unsigned len); + uint64_t clic_base_addr{0}; + unsigned clic_num_irq{0}; + unsigned clic_num_trigger{0}; + unsigned mcause_max_irq{16}; }; -template -riscv_hart_m_p::riscv_hart_m_p() +template +riscv_hart_m_p::riscv_hart_m_p() : state() , instr_if(*this) { // reset values @@ -309,32 +330,33 @@ riscv_hart_m_p::riscv_hart_m_p() csr[mvendorid] = 0x669; csr[marchid] = traits::MARCHID_VAL; csr[mimpid] = 1; + csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file uart_buf.str(""); for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){ csr_rd_cb[addr] = &this_class::read_null; } for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - //csr_wr_cb[addr] = &this_class::write_reg; + //csr_wr_cb[addr] = &this_class::write_csr_reg; } // common regs const std::array addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}}; for(auto addr: addrs) { - csr_rd_cb[addr] = &this_class::read_reg; - csr_wr_cb[addr] = &this_class::write_reg; + csr_rd_cb[addr] = &this_class::read_csr_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } // special handling & overrides csr_rd_cb[time] = &this_class::read_time; @@ -362,15 +384,23 @@ riscv_hart_m_p::riscv_hart_m_p() csr_rd_cb[mie] = &this_class::read_ie; csr_wr_cb[mie] = &this_class::write_ie; csr_rd_cb[mhartid] = &this_class::read_hartid; -// csr_rd_cb[mcounteren] = &this_class::read_null; -// csr_wr_cb[mcounteren] = &this_class::write_null; csr_wr_cb[misa] = &this_class::write_null; csr_wr_cb[mvendorid] = &this_class::write_null; csr_wr_cb[marchid] = &this_class::write_null; csr_wr_cb[mimpid] = &this_class::write_null; + if(FEAT & FEAT_DEBUG){ + csr_wr_cb[dscratch0] = &this_class::write_csr_reg; + csr_rd_cb[dscratch0] = &this_class::read_csr_reg; + csr_wr_cb[dscratch1] = &this_class::write_csr_reg; + csr_rd_cb[dscratch1] = &this_class::read_csr_reg; + csr_wr_cb[dpc] = &this_class::write_csr_reg; + csr_rd_cb[dpc] = &this_class::read_csr_reg; + csr_wr_cb[dcsr] = &this_class::write_dcsr; + csr_rd_cb[dcsr] = &this_class::read_csr_reg; + } } -template std::pair riscv_hart_m_p::load_file(std::string name, int type) { +template std::pair riscv_hart_m_p::load_file(std::string name, int type) { FILE *fp = fopen(name.c_str(), "r"); if (fp) { std::array buf; @@ -436,8 +466,8 @@ template std::pair riscv_hart_m_p::load_fi throw std::runtime_error("memory load file not found"); } -template -iss::status riscv_hart_m_p::read(const address_type type, const access_type access, const uint32_t space, +template +iss::status riscv_hart_m_p::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, uint8_t *const data) { #ifndef NDEBUG if (access && iss::access_type::DEBUG) { @@ -505,8 +535,8 @@ iss::status riscv_hart_m_p::read(const address_type type, const access_typ } } -template -iss::status riscv_hart_m_p::write(const address_type type, const access_type access, const uint32_t space, +template +iss::status riscv_hart_m_p::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, const uint8_t *const data) { #ifndef NDEBUG const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; @@ -621,7 +651,7 @@ iss::status riscv_hart_m_p::write(const address_type type, const access_ty } } -template iss::status riscv_hart_m_p::read_csr(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_csr(unsigned addr, reg_t &val) { if (addr >= csr.size()) return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; if (this->reg.PRIV < req_priv_lvl) // not having required privileges @@ -632,7 +662,7 @@ template iss::status riscv_hart_m_p::read_csr(unsigned add return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_m_p::write_csr(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_csr(unsigned addr, reg_t val) { if (addr >= csr.size()) return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; if (this->reg.PRIV < req_priv_lvl) // not having required privileges @@ -645,22 +675,22 @@ template iss::status riscv_hart_m_p::write_csr(unsigned ad return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_m_p::read_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_csr_reg(unsigned addr, reg_t &val) { val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_m_p::read_null(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_null(unsigned addr, reg_t &val) { val = 0; return iss::Ok; } -template iss::status riscv_hart_m_p::write_reg(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_csr_reg(unsigned addr, reg_t val) { csr[addr] = val; return iss::Ok; } -template iss::status riscv_hart_m_p::read_cycle(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_cycle(unsigned addr, reg_t &val) { auto cycle_val = this->reg.icount + cycle_offset; if (addr == mcycle) { val = static_cast(cycle_val); @@ -671,7 +701,7 @@ template iss::status riscv_hart_m_p::read_cycle(unsigned a return iss::Ok; } -template iss::status riscv_hart_m_p::write_cycle(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_cycle(unsigned addr, reg_t val) { if (sizeof(typename traits::reg_t) != 4) { if (addr == mcycleh) return iss::Err; @@ -687,7 +717,7 @@ template iss::status riscv_hart_m_p::write_cycle(unsigned return iss::Ok; } -template iss::status riscv_hart_m_p::read_instret(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_instret(unsigned addr, reg_t &val) { if ((addr&0xff) == (minstret&0xff)) { val = static_cast(this->reg.instret); } else if ((addr&0xff) == (minstreth&0xff)) { @@ -697,7 +727,7 @@ template iss::status riscv_hart_m_p::read_instret(unsigned return iss::Ok; } -template iss::status riscv_hart_m_p::write_instret(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_instret(unsigned addr, reg_t val) { if (sizeof(typename traits::reg_t) != 4) { if ((addr&0xff) == (minstreth&0xff)) return iss::Err; @@ -713,7 +743,7 @@ template iss::status riscv_hart_m_p::write_instret(unsigne return iss::Ok; } -template iss::status riscv_hart_m_p::read_time(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_time(unsigned addr, reg_t &val) { uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; if (addr == time) { val = static_cast(time_val); @@ -724,50 +754,50 @@ template iss::status riscv_hart_m_p::read_time(unsigned ad return iss::Ok; } -template iss::status riscv_hart_m_p::read_tvec(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_tvec(unsigned addr, reg_t &val) { val = csr[mtvec] & ~2; return iss::Ok; } -template iss::status riscv_hart_m_p::read_status(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_status(unsigned addr, reg_t &val) { val = state.mstatus & hart_state_type::get_mask(); return iss::Ok; } -template iss::status riscv_hart_m_p::write_status(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_status(unsigned addr, reg_t val) { state.write_mstatus(val); check_interrupt(); return iss::Ok; } -template iss::status riscv_hart_m_p::write_cause(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_cause(unsigned addr, reg_t val) { csr[mcause] = val & ((1UL<<(traits::XLEN-1))|0xf); //TODO: make exception code size configurable return iss::Ok; } -template iss::status riscv_hart_m_p::read_ie(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_ie(unsigned addr, reg_t &val) { val = csr[mie]; return iss::Ok; } -template iss::status riscv_hart_m_p::read_hartid(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_hartid(unsigned addr, reg_t &val) { val = mhartid_reg; return iss::Ok; } -template iss::status riscv_hart_m_p::write_ie(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_ie(unsigned addr, reg_t val) { auto mask = get_irq_mask(); csr[mie] = (csr[mie] & ~mask) | (val & mask); check_interrupt(); return iss::Ok; } -template iss::status riscv_hart_m_p::read_ip(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_ip(unsigned addr, reg_t &val) { val = csr[mip]; return iss::Ok; } -template iss::status riscv_hart_m_p::write_ip(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_ip(unsigned addr, reg_t val) { auto mask = get_irq_mask(); mask &= ~(1 << 7); // MTIP is read only csr[mip] = (csr[mip] & ~mask) | (val & mask); @@ -775,13 +805,22 @@ template iss::status riscv_hart_m_p::write_ip(unsigned add return iss::Ok; } -template iss::status riscv_hart_m_p::write_epc(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_epc(unsigned addr, reg_t val) { csr[addr] = val & get_pc_mask(); return iss::Ok; } -template -iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { +template iss::status riscv_hart_m_p::write_dcsr(unsigned addr, reg_t val) { + // +-------------- ebreakm + // | +---------- stepi + // | | +++----- cause + // | | ||| +- step + csr[addr] = val & 0b1000100111000100U; + return iss::Ok; +} + +template +iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { if(mem_read_cb) return mem_read_cb(paddr, length, data); switch (paddr.val) { case 0x0200BFF8: { // CLINT base, mtime reg @@ -805,8 +844,8 @@ iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsigned length, u return iss::Ok; } -template -iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) { +template +iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) { if(mem_write_cb) return mem_write_cb(paddr, length, data); switch (paddr.val) { case 0x10013000: // UART0 base, TXFIFO reg @@ -883,12 +922,12 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned length, return iss::Ok; } -template inline void riscv_hart_m_p::reset(uint64_t address) { +template inline void riscv_hart_m_p::reset(uint64_t address) { BASE::reset(address); state.mstatus = hart_state_type::mstatus_reset_val; } -template void riscv_hart_m_p::check_interrupt() { +template void riscv_hart_m_p::check_interrupt() { //auto ideleg = csr[mideleg]; // Multiple simultaneous interrupts and traps at the same privilege level are // handled in the following decreasing priority order: @@ -910,14 +949,14 @@ template void riscv_hart_m_p::check_interrupt() { } } -template uint64_t riscv_hart_m_p::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) { +template uint64_t riscv_hart_m_p::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) { // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // calculate and write mcause val auto trap_id = bit_sub<0, 16>(flags); auto cause = bit_sub<16, 15>(flags); - if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause // calculate effective privilege level if (trap_id == 0) { // exception + if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause // store ret addr in xepc register csr[mepc] = static_cast(addr) & get_pc_mask(); // store actual address instruction of exception switch(cause){ @@ -927,6 +966,12 @@ template uint64_t riscv_hart_m_p::enter_trap(uint64_t flag case 2: csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff; break; + case 3: + //TODO: implement debug mode behavior + // csr[dpc] = addr; + // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi) + csr[mtval] = addr; + break; default: csr[mtval] = fault_data; } @@ -969,7 +1014,7 @@ template uint64_t riscv_hart_m_p::enter_trap(uint64_t flag return this->reg.NEXT_PC; } -template uint64_t riscv_hart_m_p::leave_trap(uint64_t flags) { +template uint64_t riscv_hart_m_p::leave_trap(uint64_t flags) { state.mstatus.MIE = state.mstatus.MPIE; state.mstatus.MPIE = 1; // sets the pc to the value stored in the x epc register. diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h index 86bd720..bb25f2e 100644 --- a/incl/iss/arch/riscv_hart_mu_p.h +++ b/incl/iss/arch/riscv_hart_mu_p.h @@ -66,8 +66,6 @@ namespace iss { namespace arch { -enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N, FEAT_CLIC}; - template class riscv_hart_mu_p : public BASE { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; @@ -326,6 +324,7 @@ private: iss::status write_edeleg(unsigned addr, reg_t val); iss::status read_hartid(unsigned addr, reg_t &val); iss::status write_epc(unsigned addr, reg_t val); + iss::status write_dcsr(unsigned addr, reg_t val); iss::status write_intstatus(unsigned addr, reg_t val); iss::status write_intthresh(unsigned addr, reg_t val); @@ -464,6 +463,16 @@ riscv_hart_mu_p::riscv_hart_mu_p() clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq; mcause_max_irq=clic_num_irq+16; } + if(FEAT & FEAT_DEBUG){ + csr_wr_cb[dscratch0] = &this_class::write_csr_reg; + csr_rd_cb[dscratch0] = &this_class::read_csr_reg; + csr_wr_cb[dscratch1] = &this_class::write_csr_reg; + csr_rd_cb[dscratch1] = &this_class::read_csr_reg; + csr_wr_cb[dpc] = &this_class::write_csr_reg; + csr_rd_cb[dpc] = &this_class::read_csr_reg; + csr_wr_cb[dcsr] = &this_class::write_dcsr; + csr_rd_cb[dcsr] = &this_class::read_csr_reg; + } } template std::pair riscv_hart_mu_p::load_file(std::string name, int type) { @@ -968,6 +977,14 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::write_dcsr(unsigned addr, reg_t val) { + // +-------------- ebreakm + // | +---------- stepi + // | | +++----- cause + // | | ||| +- step + csr[addr] = val & 0b1000100111000100U; + return iss::Ok; +} template iss::status riscv_hart_mu_p::write_intthresh(unsigned addr, reg_t val) { csr[addr]= val &0xff;