fix compiler warning for reduced number of registers
This commit is contained in:
parent
5ec457c76b
commit
d91f5f9df4
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@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
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static constexpr std::array<const char*, 36> reg_aliases{
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{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
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enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
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enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
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constexpr static unsigned FP_REGS_SIZE = 0;
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@ -214,12 +214,26 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
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auto start_reg=arch::traits<ARCH>::X0;
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auto *reg_base = core->get_regs_base_ptr();
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auto iter = data.data();
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bool e_ext = arch::traits<ARCH>::PC<32;
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for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
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std::copy(iter, iter + reg_width, reg_base);
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iter += 4;
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reg_base += offset;
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if(e_ext && reg_no>15){
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if(reg_no==32){
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
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std::copy(iter, iter + reg_width, reg_base);
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} else {
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const uint64_t zero_val=0;
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
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auto iter = (uint8_t*)&zero_val;
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std::copy(iter, iter + reg_width, reg_base);
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}
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} else {
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
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std::copy(iter, iter + reg_width, reg_base);
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iter += 4;
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reg_base += offset;
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}
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}
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return Ok;
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}
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@ -397,7 +397,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = (int32_t)imm;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)imm;
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} catch(...){}
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}
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break;
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@ -417,7 +417,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = *PC + (int32_t)imm;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *PC + (int32_t)imm;
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} catch(...){}
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}
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break;
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@ -439,10 +439,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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try {
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{
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if(imm % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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raise(0, 0);
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}
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else {
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if(rd != 0) *(X+rd) = *PC + 4;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *PC + 4;
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pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
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}
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}
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@ -467,12 +467,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1;
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int32_t new_pc = (*(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm)) & ~ 1;
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if(new_pc % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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raise(0, 0);
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}
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else {
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if(rd != 0) *(X+rd) = *PC + 4;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *PC + 4;
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pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
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}
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}
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@ -497,8 +497,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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if(*(X+rs1 % traits::RFS) == *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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else {
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pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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@ -525,8 +525,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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if(*(X+rs1 % traits::RFS) != *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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else {
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pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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@ -553,8 +553,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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if((int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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else {
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pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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@ -581,8 +581,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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if((int32_t)*(X+rs1 % traits::RFS) >= (int32_t)*(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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else {
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pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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@ -609,8 +609,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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if(*(X+rs1 % traits::RFS) < *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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else {
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pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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@ -637,8 +637,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
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raise( 0, 0);
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if(*(X+rs1 % traits::RFS) >= *(X+rs2 % traits::RFS)) if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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else {
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pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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@ -665,8 +665,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
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if(rd != 0) *(X+rd) = res;
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int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm));
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
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}
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} catch(...){}
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}
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@ -689,9 +689,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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int16_t res = (int16_t)readSpace2(traits::MEM, load_address);
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if(rd != 0) *(X+rd) = res;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
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}
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} catch(...){}
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}
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@ -714,9 +714,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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int32_t res = (int32_t)readSpace4(traits::MEM, load_address);
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if(rd != 0) *(X+rd) = (uint32_t)res;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (uint32_t)res;
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}
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} catch(...){}
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}
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@ -739,8 +739,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
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if(rd != 0) *(X+rd) = res;
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uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm));
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
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}
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} catch(...){}
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}
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@ -763,9 +763,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint16_t res = (uint16_t)readSpace2(traits::MEM, load_address);
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if(rd != 0) *(X+rd) = res;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = res;
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}
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} catch(...){}
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}
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@ -787,7 +787,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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writeSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2));
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writeSpace1(traits::MEM, *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2 % traits::RFS));
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} catch(...){}
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}
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break;
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@ -809,8 +809,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
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writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2));
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2 % traits::RFS));
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}
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} catch(...){}
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}
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@ -833,8 +833,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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{
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uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
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writeSpace4(traits::MEM, store_address, *(X+rs2));
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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writeSpace4(traits::MEM, store_address, *(X+rs2 % traits::RFS));
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}
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} catch(...){}
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}
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@ -856,7 +856,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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} catch(...){}
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}
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break;
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@ -877,7 +877,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)sext<12>(imm)? 1 : 0;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) < (int16_t)sext<12>(imm)? 1 : 0;
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} catch(...){}
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}
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break;
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@ -898,7 +898,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (*(X+rs1 % traits::RFS) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
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} catch(...){}
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}
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break;
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@ -919,7 +919,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)sext<12>(imm);
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) ^ (int16_t)sext<12>(imm);
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} catch(...){}
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}
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break;
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@ -940,7 +940,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)sext<12>(imm);
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) | (int16_t)sext<12>(imm);
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} catch(...){}
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}
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break;
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@ -961,7 +961,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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try {
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if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)sext<12>(imm);
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) & (int16_t)sext<12>(imm);
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} catch(...){}
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}
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break;
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@ -983,10 +983,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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if(shamt > 31) {
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raise( 0, 0);
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raise(0, 0);
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}
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else {
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if(rd != 0) *(X+rd) = *(X+rs1) << shamt;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) << shamt;
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}
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} catch(...){}
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}
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@ -1009,10 +1009,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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if(shamt > 31) {
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raise( 0, 0);
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raise(0, 0);
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}
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else {
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if(rd != 0) *(X+rd) = *(X+rs1) >> shamt;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) >> shamt;
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}
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} catch(...){}
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}
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@ -1035,10 +1035,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// execute instruction
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try {
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if(shamt > 31) {
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raise( 0, 0);
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raise(0, 0);
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}
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else {
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if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> shamt;
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if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) >> shamt;
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}
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} catch(...){}
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}
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||||
|
@ -1060,7 +1060,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs1) + *(X+rs2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) + *(X+rs2 % traits::RFS);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1081,7 +1081,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs1) - *(X+rs2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) - *(X+rs2 % traits::RFS);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1102,7 +1102,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) << (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1123,7 +1123,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)? 1 : 0;
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1144,7 +1144,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = (uint32_t)*(X+rs1) < (uint32_t)*(X+rs2)? 1 : 0;
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (uint32_t)*(X+rs1 % traits::RFS) < (uint32_t)*(X+rs2 % traits::RFS)? 1 : 0;
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1165,7 +1165,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs1) ^ *(X+rs2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) ^ *(X+rs2 % traits::RFS);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1186,7 +1186,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1207,7 +1207,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1228,7 +1228,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs1) | *(X+rs2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) | *(X+rs2 % traits::RFS);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1249,7 +1249,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs1) & *(X+rs2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) & *(X+rs2 % traits::RFS);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1285,7 +1285,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
raise( 0, 11);
|
||||
raise(0, 11);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1299,7 +1299,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
raise( 0, 3);
|
||||
raise(0, 3);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1313,7 +1313,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
leave( 0);
|
||||
leave(0);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1327,7 +1327,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
leave( 1);
|
||||
leave(1);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1341,7 +1341,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
leave( 3);
|
||||
leave(3);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1355,7 +1355,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
wait( 1);
|
||||
wait(1);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1374,7 +1374,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(*PRIV < 4) raise( 0, 2);
|
||||
if(*PRIV < 4) raise(0, 2);
|
||||
else {
|
||||
pc_assign(*NEXT_PC) = *DPC;
|
||||
*PRIV &= 0x3;
|
||||
|
@ -1401,11 +1401,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
if(rd != 0) {
|
||||
uint32_t xrs1 = *(X+rs1 % traits::RFS);
|
||||
if((rd % traits::RFS) != 0) {
|
||||
uint32_t xrd = readSpace4(traits::CSR, csr);
|
||||
writeSpace4(traits::CSR, csr, xrs1);
|
||||
*(X+rd) = xrd;
|
||||
*(X+rd % traits::RFS) = xrd;
|
||||
}
|
||||
else {
|
||||
writeSpace4(traits::CSR, csr, xrs1);
|
||||
|
@ -1433,9 +1433,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
try {
|
||||
{
|
||||
uint32_t xrd = readSpace4(traits::CSR, csr);
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
uint32_t xrs1 = *(X+rs1 % traits::RFS);
|
||||
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd | xrs1);
|
||||
if(rd != 0) *(X+rd) = xrd;
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -1459,9 +1459,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
try {
|
||||
{
|
||||
uint32_t xrd = readSpace4(traits::CSR, csr);
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
uint32_t xrs1 = *(X+rs1 % traits::RFS);
|
||||
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd & ~ xrs1);
|
||||
if(rd != 0) *(X+rd) = xrd;
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -1486,7 +1486,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
{
|
||||
uint32_t xrd = readSpace4(traits::CSR, csr);
|
||||
writeSpace4(traits::CSR, csr, (uint32_t)zimm);
|
||||
if(rd != 0) *(X+rd) = xrd;
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -1511,7 +1511,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
{
|
||||
uint32_t xrd = readSpace4(traits::CSR, csr);
|
||||
if(zimm != 0) writeSpace4(traits::CSR, csr, xrd | (uint32_t)zimm);
|
||||
if(rd != 0) *(X+rd) = xrd;
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -1536,7 +1536,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
{
|
||||
uint32_t xrd = readSpace4(traits::CSR, csr);
|
||||
if(zimm != 0) writeSpace4(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
|
||||
if(rd != 0) *(X+rd) = xrd;
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = xrd;
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -1579,9 +1579,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
|
||||
*(X+rd) = (uint32_t)res;
|
||||
if((rd % traits::RFS) != 0) {
|
||||
int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (int64_t)(int32_t)*(X+rs2 % traits::RFS);
|
||||
*(X+rd % traits::RFS) = (uint32_t)res;
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1605,9 +1605,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
|
||||
*(X+rd) = (uint32_t)(res >> traits::XLEN);
|
||||
if((rd % traits::RFS) != 0) {
|
||||
int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (int64_t)(int32_t)*(X+rs2 % traits::RFS);
|
||||
*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1631,9 +1631,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
|
||||
*(X+rd) = (uint32_t)(res >> traits::XLEN);
|
||||
if((rd % traits::RFS) != 0) {
|
||||
int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (uint64_t)*(X+rs2 % traits::RFS);
|
||||
*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1657,9 +1657,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
|
||||
*(X+rd) = (uint32_t)(res >> traits::XLEN);
|
||||
if((rd % traits::RFS) != 0) {
|
||||
uint64_t res = (uint64_t)*(X+rs1 % traits::RFS) * (uint64_t)*(X+rs2 % traits::RFS);
|
||||
*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1683,13 +1683,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
if(*(X+rs2) != 0) {
|
||||
if((rd % traits::RFS) != 0) {
|
||||
if(*(X+rs2 % traits::RFS) != 0) {
|
||||
uint32_t MMIN = 1 << (traits::XLEN - 1);
|
||||
if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = MMIN;
|
||||
else *(X+rd) = (int32_t)*(X+rs1) / (int32_t)*(X+rs2);
|
||||
if(*(X+rs1 % traits::RFS) == MMIN && (int32_t)*(X+rs2 % traits::RFS) == - 1) *(X+rd % traits::RFS) = MMIN;
|
||||
else *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) / (int32_t)*(X+rs2 % traits::RFS);
|
||||
}
|
||||
else *(X+rd) = - 1;
|
||||
else *(X+rd % traits::RFS) = - 1;
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1713,9 +1713,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) / *(X+rs2);
|
||||
else *(X+rd) = - 1;
|
||||
if((rd % traits::RFS) != 0) {
|
||||
if(*(X+rs2 % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) / *(X+rs2 % traits::RFS);
|
||||
else *(X+rd % traits::RFS) = - 1;
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1739,13 +1739,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
if(*(X+rs2) != 0) {
|
||||
if((rd % traits::RFS) != 0) {
|
||||
if(*(X+rs2 % traits::RFS) != 0) {
|
||||
uint32_t MMIN = 1 << (traits::XLEN - 1);
|
||||
if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = 0;
|
||||
else *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
|
||||
if(*(X+rs1 % traits::RFS) == MMIN && (int32_t)*(X+rs2 % traits::RFS) == - 1) *(X+rd % traits::RFS) = 0;
|
||||
else *(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) % (int32_t)*(X+rs2 % traits::RFS);
|
||||
}
|
||||
else *(X+rd) = *(X+rs1);
|
||||
else *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS);
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1769,9 +1769,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) {
|
||||
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) % *(X+rs2);
|
||||
else *(X+rd) = *(X+rs1);
|
||||
if((rd % traits::RFS) != 0) {
|
||||
if(*(X+rs2 % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) % *(X+rs2 % traits::RFS);
|
||||
else *(X+rd % traits::RFS) = *(X+rs1 % traits::RFS);
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
|
@ -1794,7 +1794,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
if(imm) *(X+rd + 8) = *(X+2) + imm;
|
||||
else raise( 0, 2);
|
||||
else raise(0, 2);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1862,7 +1862,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
*(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
|
||||
*(X+rs1 % traits::RFS) = *(X+rs1 % traits::RFS) + (int8_t)sext<6>(imm);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1921,7 +1921,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm);
|
||||
if((rd % traits::RFS) != 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -1943,8 +1943,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(imm == 0) raise( 0, 2);
|
||||
if(rd != 0) *(X+rd) = (int32_t)sext<18>(imm);
|
||||
if(imm == 0) raise(0, 2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int32_t)sext<18>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -1965,7 +1965,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
if(nzimm) *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm);
|
||||
else raise( 0, 2);
|
||||
else raise(0, 2);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -1980,7 +1980,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
raise( 0, 2);
|
||||
raise(0, 2);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2223,7 +2223,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
if(nzuimm) *(X+rs1) = *(X+rs1) << nzuimm;
|
||||
if(nzuimm) *(X+rs1 % traits::RFS) = *(X+rs1 % traits::RFS) << nzuimm;
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2245,9 +2245,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
try {
|
||||
if(rd) {
|
||||
uint32_t offs = *(X+2) + uimm;
|
||||
*(X+rd) = (int32_t)readSpace4(traits::MEM, offs);
|
||||
*(X+rd % traits::RFS) = (int32_t)readSpace4(traits::MEM, offs);
|
||||
}
|
||||
else raise( 0, 2);
|
||||
else raise(0, 2);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2267,7 +2267,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rs2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rs2 % traits::RFS);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2286,8 +2286,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rs1) pc_assign(*NEXT_PC) = *(X+rs1) & ~ 0x1;
|
||||
else raise( 0, 2);
|
||||
if(rs1) pc_assign(*NEXT_PC) = *(X+rs1 % traits::RFS) & ~ 0x1;
|
||||
else raise(0, 2);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2301,7 +2301,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
raise( 0, 2);
|
||||
raise(0, 2);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2321,7 +2321,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
if(rd != 0) *(X+rd) = *(X+rd) + *(X+rs2);
|
||||
if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = *(X+rd % traits::RFS) + *(X+rs2 % traits::RFS);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2341,7 +2341,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
// execute instruction
|
||||
try {
|
||||
{
|
||||
int32_t new_pc = *(X+rs1);
|
||||
int32_t new_pc = *(X+rs1 % traits::RFS);
|
||||
*(X+1) = *PC + 2;
|
||||
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
|
||||
}
|
||||
|
@ -2358,7 +2358,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
raise( 0, 3);
|
||||
raise(0, 3);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
@ -2380,7 +2380,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
try {
|
||||
{
|
||||
uint32_t offs = *(X+2) + uimm;
|
||||
writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2));
|
||||
writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2 % traits::RFS));
|
||||
}
|
||||
} catch(...){}
|
||||
}
|
||||
|
@ -2395,7 +2395,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
try {
|
||||
raise( 0, 2);
|
||||
raise(0, 2);
|
||||
} catch(...){}
|
||||
}
|
||||
break;
|
||||
|
|
Loading…
Reference in New Issue