removes v2p function
This commit is contained in:
parent
e151416f58
commit
20e920338c
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@ -70,7 +70,7 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
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}
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@ -137,14 +137,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
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inline uint64_t stop_code() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
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} else
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return virt2phys(addr);
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}
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virtual phys_addr_t virt2phys(const iss::addr_t& addr);
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virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
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@ -666,7 +666,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
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fault_data=addr;
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return iss::Err;
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}
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auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
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phys_addr_t phys_addr{access, space, addr};
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auto res = iss::Err;
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if(access != access_type::FETCH && memfn_range.size()){
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auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
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@ -759,7 +759,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
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fault_data=addr;
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return iss::Err;
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}
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auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
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phys_addr_t phys_addr{access, space, addr};
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auto res = iss::Err;
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if(access != access_type::FETCH && memfn_range.size()){
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auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
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@ -784,9 +784,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
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return iss::Err;
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}
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phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
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if ((paddr.val + length) > mem.size()) return iss::Err;
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switch (paddr.val) {
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if ((addr + length) > mem.size()) return iss::Err;
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switch (addr) {
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case 0x10013000: // UART0 base, TXFIFO reg
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case 0x10023000: // UART1 base, TXFIFO reg
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uart_buf << (char)data[0];
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@ -798,16 +797,16 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
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}
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return iss::Ok;
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case 0x10008000: { // HFROSC base, hfrosccfg reg
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auto &p = mem(paddr.val / mem.page_size);
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auto offs = paddr.val & mem.page_addr_mask;
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auto &p = mem(addr / mem.page_size);
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auto offs = addr & mem.page_addr_mask;
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std::copy(data, data + length, p.data() + offs);
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auto &x = *(p.data() + offs + 3);
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if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
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return iss::Ok;
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}
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case 0x10008008: { // HFROSC base, pllcfg reg
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auto &p = mem(paddr.val / mem.page_size);
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auto offs = paddr.val & mem.page_addr_mask;
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auto &p = mem(addr / mem.page_size);
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auto offs = addr & mem.page_addr_mask;
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std::copy(data, data + length, p.data() + offs);
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auto &x = *(p.data() + offs + 3);
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x |= 0x80; // set pll lock upon writing
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@ -430,6 +430,7 @@ template <typename BASE>
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riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
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: state()
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, instr_if(*this) {
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this->_has_mmu = true;
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// reset values
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csr[misa] = traits<BASE>::MISA_VAL;
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csr[mvendorid] = 0x669;
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@ -632,9 +633,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
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return res;
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}
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}
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auto res = type==iss::address_type::PHYSICAL?
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read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
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read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
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auto res = read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
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if (unlikely(res != iss::Ok)){
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this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
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fault_data=addr;
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@ -719,6 +718,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
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this->reg.trap_state = (1 << 31); // issue trap 0
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return iss::Err;
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}
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phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
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try {
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if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
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vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
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@ -731,9 +731,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
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return res;
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}
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}
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auto res = type==iss::address_type::PHYSICAL?
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write_mem(phys_addr_t{access, space, addr}, length, data):
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write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
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auto res = write_mem(paddr, length, data);
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if (unlikely(res != iss::Ok)) {
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this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
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fault_data=addr;
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@ -745,7 +743,6 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
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return iss::Err;
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}
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phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
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if ((paddr.val + length) > mem.size()) return iss::Err;
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switch (paddr.val) {
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case 0x10013000: // UART0 base, TXFIFO reg
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@ -834,7 +834,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
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fault_data=addr;
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return iss::Err;
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}
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auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
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phys_addr_t phys_addr{access, space, addr};
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auto res = iss::Err;
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if(!is_fetch(access) && memfn_range.size()){
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auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
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@ -935,7 +935,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
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fault_data=addr;
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return iss::Err;
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}
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auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
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phys_addr_t phys_addr{access, space, addr};
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auto res = iss::Err;
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if(!is_fetch(access) && memfn_range.size()){
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auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
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@ -960,30 +960,29 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
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return iss::Err;
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}
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phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
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if ((paddr.val + length) > mem.size()) return iss::Err;
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switch (paddr.val) {
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if ((addr + length) > mem.size()) return iss::Err;
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switch (addr) {
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case 0x10013000: // UART0 base, TXFIFO reg
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case 0x10023000: // UART1 base, TXFIFO reg
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uart_buf << (char)data[0];
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if (((char)data[0]) == '\n' || data[0] == 0) {
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// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
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// LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send
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// '"<<uart_buf.str()<<"'";
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std::cout << uart_buf.str();
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uart_buf.str("");
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}
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return iss::Ok;
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case 0x10008000: { // HFROSC base, hfrosccfg reg
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auto &p = mem(paddr.val / mem.page_size);
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auto offs = paddr.val & mem.page_addr_mask;
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auto &p = mem(addr / mem.page_size);
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auto offs = addr & mem.page_addr_mask;
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std::copy(data, data + length, p.data() + offs);
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auto &x = *(p.data() + offs + 3);
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if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
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return iss::Ok;
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}
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case 0x10008008: { // HFROSC base, pllcfg reg
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auto &p = mem(paddr.val / mem.page_size);
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auto offs = paddr.val & mem.page_addr_mask;
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auto &p = mem(addr / mem.page_size);
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auto offs = addr & mem.page_addr_mask;
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std::copy(data, data + length, p.data() + offs);
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auto &x = *(p.data() + offs + 3);
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x |= 0x80; // set pll lock upon writing
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@ -63,7 +63,7 @@ uint8_t *tgc_c::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &addr) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
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}
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@ -195,14 +195,6 @@ struct tgc_c: public arch_if {
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inline uint64_t stop_code() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
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} else
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return virt2phys(addr);
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}
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virtual phys_addr_t virt2phys(const iss::addr_t& addr);
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virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
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@ -262,7 +254,6 @@ struct tgc_c: public arch_if {
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uint32_t get_fcsr(){return 0;}
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void set_fcsr(uint32_t val){}
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};
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}
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@ -259,15 +259,22 @@ private:
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}};
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iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
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auto phys_pc = this->core.v2p(pc);
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//TODO: re-add page handling
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//if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
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// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
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// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
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//} else {
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if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err;
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//}
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if(this->core.has_mmu()) {
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auto phys_pc = this->core.virt2phys(pc);
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// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
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// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
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// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
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// return iss::Err;
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// } else {
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if (this->core.read(phys_pc, 4, data) != iss::Ok)
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return iss::Err;
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// }
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} else {
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if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
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return iss::Err;
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}
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return iss::Ok;
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}
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void populate_decoding_tree(decoding_tree_node* root){
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@ -4085,7 +4085,8 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
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// const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
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phys_addr_t paddr(pc);
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auto *const data = (uint8_t *)&insn;
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paddr = this->core.v2p(pc);
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if(this->core.has_mmu())
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paddr = this->core.virt2phys(pc);
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//TODO: re-add page handling
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// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// auto res = this->core.read(paddr, 2, data);
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@ -3174,7 +3174,8 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
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enum {TRAP_ID=1<<16};
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code_word_t instr = 0;
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phys_addr_t paddr(pc);
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paddr = this->core.v2p(pc);
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if(this->core.has_mmu())
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paddr = this->core.virt2phys(pc);
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//TODO: re-add page handling
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// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// auto res = this->core.read(paddr, 2, data);
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