DBT-RISE/DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

fixes cause CSR handling

Browse Source
This commit is contained in:
Eyck Jentzsch 2023-06-12 17:38:56 +02:00
parent 99a9970ddd
commit 4dbc7433a5
2 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/iss/arch/riscv_hart_m_p.h
View File

@ -959,14 +959,13 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cause(unsigned addr, reg_t &val) {
auto res = csr[addr];
if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
val |= clic_mprev_lvl<<16;
val |= state.mstatus.MPIE<<27;
val |= state.mstatus.MPP<<28;
} else
val = csr[addr]; // & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
return iss::Ok;
}

2
src/iss/arch/riscv_hart_mu_p.h
View File

@ -1149,7 +1149,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
break;
}
} else
val = csr[addr];// & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
return iss::Ok;
}