diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index beb0cc2..40e0ab8 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -959,14 +959,13 @@ template iss::status riscv_hart_m_p } template iss::status riscv_hart_m_p::read_cause(unsigned addr, reg_t &val) { - auto res = csr[addr]; if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) { val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16)); val |= clic_mprev_lvl<<16; val |= state.mstatus.MPIE<<27; val |= state.mstatus.MPP<<28; } else - val = csr[addr]; // & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); + val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); return iss::Ok; } diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 9650ee5..1d65c68 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -1149,7 +1149,7 @@ template iss::status riscv_hart_mu_p::XLEN-1)) | (mcause_max_irq-1)); + val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); return iss::Ok; }