DBT-RISE/DBT-RISE-TGC
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debugger memory accesses should never lead to traps

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This commit is contained in:
Stanislaw Kaushanski 2023-10-06 21:39:48 +02:00
parent ee6a068b06
commit 9180ad1f9c
3 changed files with 6 additions and 6 deletions
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4
src/iss/arch/riscv_hart_m_p.h
View File

@ -682,7 +682,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
} else {
res = hart_mem_rd_delegate( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)){
if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr;
}
@ -775,7 +775,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
} else {
res = write_mem( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)) {
if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr;
}

4
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -636,7 +636,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
}
}
auto res = read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
if (unlikely(res != iss::Ok)){
if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr;
}
@ -734,7 +734,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
}
}
auto res = write_mem(paddr, length, data);
if (unlikely(res != iss::Ok)) {
if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr;
}

4
src/iss/arch/riscv_hart_mu_p.h
View File

@ -850,7 +850,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
} else {
res = hart_mem_rd_delegate( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)){
if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr;
}
@ -951,7 +951,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
} else {
res = hart_mem_wr_delegate( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)) {
if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr;
}