From 9180ad1f9c0af678e6080b3fd0db6727213a99eb Mon Sep 17 00:00:00 2001
From: Stanislaw Kaushanski <stas@minres.com>
Date: Fri, 6 Oct 2023 21:39:48 +0200
Subject: [PATCH] debugger memory accesses should never lead to traps

---
 src/iss/arch/riscv_hart_m_p.h    | 4 ++--
 src/iss/arch/riscv_hart_msu_vp.h | 4 ++--
 src/iss/arch/riscv_hart_mu_p.h   | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 935c774..26e327d 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -682,7 +682,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                 } else {
                     res = hart_mem_rd_delegate( phys_addr, length, data);
                 }
-                if (unlikely(res != iss::Ok)){
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
                     this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
@@ -775,7 +775,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                 } else {
                     res = write_mem( phys_addr, length, data);
                 }
-                if (unlikely(res != iss::Ok)) {
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 9627eff..56c7209 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -636,7 +636,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                     }
                 }
                 auto res = read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)){
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
                 	this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
@@ -734,7 +734,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                     }
                 }
                 auto res = write_mem(paddr, length, data);
-                if (unlikely(res != iss::Ok)) {
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 48cf106..33089af 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -850,7 +850,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                 } else {
                     res = hart_mem_rd_delegate( phys_addr, length, data);
                 }
-                if (unlikely(res != iss::Ok)){
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
                     this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
@@ -951,7 +951,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                 } else {
                     res = hart_mem_wr_delegate( phys_addr, length, data);
                 }
-                if (unlikely(res != iss::Ok)) {
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }