fix stand-alone ISS compilation to include all generated cores
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6f8595759e
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@ -146,15 +146,11 @@ if(SystemC_FOUND)
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add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
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target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
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target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
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if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
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target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
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endif()
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if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
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target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
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endif()
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if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
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target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
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endif()
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foreach(F IN LISTS TGC_SOURCES)
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string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
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string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
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target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
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endforeach()
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target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
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if(WITH_LLVM)
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target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
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@ -1,9 +1,9 @@
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{
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{
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"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
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{
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"name" : "${instr.name}",
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"size" : ${instr.length},
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"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
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"delay" : ${instr.isConditional?"[1,1]":"1"}
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}<%}%>
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]
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}
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@ -57,6 +57,11 @@ using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::
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#include "iss/arch/tgc_d_xrb_mac.h"
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using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, iss::arch::FEAT_PMP>;
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#endif
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#ifdef CORE_TGC_D_XRB_NN
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#include "iss/arch/riscv_hart_mu_p.h"
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#include "iss/arch/tgc_d_xrb_nn.h"
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using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, iss::arch::FEAT_PMP>;
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#endif
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#include <scc/report.h>
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#include <util/ities.h>
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#include <iostream>
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@ -303,8 +308,11 @@ public:
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#ifdef CORE_TGC_D
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CREATE_CORE(tgc_d)
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#endif
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#ifdef CORE_TGC_D_XRB_MACD
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#ifdef CORE_TGC_D_XRB_MAC
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CREATE_CORE(tgc_d_xrb_mac)
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#endif
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#ifdef CORE_TGC_D_XRB_NN
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CREATE_CORE(tgc_d_xrb_nn)
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#endif
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{
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LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
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