From 07d5af1ddef14b4d7a17db376f944dddb341184f Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 26 Nov 2021 17:56:40 +0100
Subject: [PATCH] fix stand-alone ISS compilation to include all generated
 cores

---
 CMakeLists.txt                             | 14 +++++---------
 gen_input/templates/CORENAME_cyles.txt.gtl |  4 ++--
 src/sysc/core_complex.cpp                  | 10 +++++++++-
 3 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index e0fd2c9..aec662a 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -146,15 +146,11 @@ if(SystemC_FOUND)
     add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
-    endif()
+    foreach(F IN LISTS TGC_SOURCES)
+        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    endforeach()
     target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
     if(WITH_LLVM)
         target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
diff --git a/gen_input/templates/CORENAME_cyles.txt.gtl b/gen_input/templates/CORENAME_cyles.txt.gtl
index 3a1ad8e..6e8bbf7 100644
--- a/gen_input/templates/CORENAME_cyles.txt.gtl
+++ b/gen_input/templates/CORENAME_cyles.txt.gtl
@@ -1,9 +1,9 @@
-{ 
+{
 	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
 		{
 			"name"  : "${instr.name}",
 			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+			"delay" : ${instr.isConditional?"[1,1]":"1"}
 		}<%}%>
 	]
 }
\ No newline at end of file
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 268c9e8..ed21bb8 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -57,6 +57,11 @@ using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::
 #include "iss/arch/tgc_d_xrb_mac.h"
 using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, iss::arch::FEAT_PMP>;
 #endif
+#ifdef CORE_TGC_D_XRB_NN
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_d_xrb_nn.h"
+using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, iss::arch::FEAT_PMP>;
+#endif
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
@@ -303,8 +308,11 @@ public:
 #ifdef CORE_TGC_D
         CREATE_CORE(tgc_d)
 #endif
-#ifdef CORE_TGC_D_XRB_MACD
+#ifdef CORE_TGC_D_XRB_MAC
         CREATE_CORE(tgc_d_xrb_mac)
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        CREATE_CORE(tgc_d_xrb_nn)
 #endif
         {
             LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;