DBT-RISE/DBT-RISE-TGC
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updates generated files

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Eyck-Alexander Jentzsch 2024-07-10 12:55:36 +02:00
parent ac8f8b0539
commit 149b3136d2
3 changed files with 7 additions and 5 deletions
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2
src/iss/arch/tgc5c.h
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File diff suppressed because one or more lines are too long

2
src/vm/asmjit/vm_tgc5c.cpp
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@ -4809,4 +4809,4 @@ volatile std::array<bool, 2> dummy = {
};
}
}
// clang-format on
// clang-format on

8
src/vm/interp/vm_tgc5c.cpp
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 20217-2024 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -2534,7 +2534,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 && rs1 < traits::RFS) {
*NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 1 );
uint32_t addr_mask = (uint32_t)- 2;
*NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & addr_mask;
this->core.reg.last_branch = 1;
}
else {
@ -2600,9 +2601,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t addr_mask = (uint32_t)- 2;
uint32_t new_pc = *(X+rs1);
*(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 ));
*NEXT_PC = new_pc & (uint32_t)(~ 1 );
*NEXT_PC = new_pc & addr_mask;
this->core.reg.last_branch = 1;
}
}