applies clang-format fixes
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@ -417,7 +417,7 @@ protected:
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std::vector<std::function<mem_write_f>> memfn_write;
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void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
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feature_config cfg;
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unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U,static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U};
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unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U, static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U};
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inline bool debug_mode_active() { return this->reg.PRIV & 0x4; }
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std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd,
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std::function<mem_write_f> wr) {
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@ -824,8 +824,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
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x |= 0x80; // set pll lock upon writing
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return iss::Ok;
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} break;
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default: {
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}
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default: {}
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}
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} break;
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case traits<BASE>::CSR: {
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@ -804,8 +804,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
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x |= 0x80; // set pll lock upon writing
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return iss::Ok;
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} break;
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default: {
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}
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default: {}
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}
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} break;
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case traits<BASE>::CSR: {
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@ -1228,9 +1227,9 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
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break;
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} else if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
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break;
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} else if(type == iss::access_type::FETCH ? !(pte & PTE_X)
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: type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
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: !((pte & PTE_R) && (pte & PTE_W))) {
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} else if(type == (iss::access_type::FETCH ? !(pte & PTE_X)
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: type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
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: !((pte & PTE_R) && (pte & PTE_W)))) {
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break;
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} else if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
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break;
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@ -447,7 +447,7 @@ protected:
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std::vector<std::function<mem_write_f>> memfn_write;
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void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
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feature_config cfg;
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unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U,static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U};
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unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U, static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U};
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inline bool debug_mode_active() { return this->reg.PRIV & 0x4; }
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std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd,
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@ -1007,8 +1007,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
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x |= 0x80; // set pll lock upon writing
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return iss::Ok;
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} break;
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default: {
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}
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default: {}
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}
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} break;
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case traits<BASE>::CSR: {
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