DBT-RISE/DBT-RISE-TGC
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checkin: tgc5f builds and runs through

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This commit is contained in:
Eyck-Alexander Jentzsch 2024-07-28 15:36:12 +02:00
parent a365110054
commit 39d2518fdd
2 changed files with 17 additions and 1 deletions
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7
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -100,7 +100,12 @@ protected:
using compile_ret_t = virt_addr_t;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%
def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}%>
virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;

11
src/iss/arch/riscv_hart_m_p.h
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@ -39,6 +39,7 @@
#include "iss/instrumentation_if.h"
#include "iss/log_categories.h"
#include "iss/vm_if.h"
#include "iss/vm_types.h"
#include "riscv_hart_common.h"
#include <stdexcept>
#ifndef FMT_HEADER_ONLY
@ -691,6 +692,11 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
case traits<BASE>::CSR: {
if(length != sizeof(reg_t))
return iss::Err;
// We emulate the FCSR in the architectural state
if(addr == 3) {
*data = this->get_fcsr();
return iss::Ok;
}
return read_csr(addr, *reinterpret_cast<reg_t* const>(data));
} break;
case traits<BASE>::FENCE: {
@ -822,6 +828,11 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
case traits<BASE>::CSR: {
if(length != sizeof(reg_t))
return iss::Err;
// We emulate the FCSR in the architectural state
if(addr == 3) {
this->set_fcsr(*data);
return iss::Ok;
}
return write_csr(addr, *reinterpret_cast<const reg_t*>(data));
} break;
case traits<BASE>::FENCE: {