checkin: tgc5f builds and runs through
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a365110054
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@ -100,7 +100,12 @@ protected:
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using compile_ret_t = virt_addr_t;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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<%
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def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
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<%}%>
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virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
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@ -39,6 +39,7 @@
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#include "iss/instrumentation_if.h"
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#include "iss/log_categories.h"
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#include "iss/vm_if.h"
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#include "iss/vm_types.h"
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#include "riscv_hart_common.h"
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#include <stdexcept>
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#ifndef FMT_HEADER_ONLY
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@ -691,6 +692,11 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
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case traits<BASE>::CSR: {
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if(length != sizeof(reg_t))
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return iss::Err;
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// We emulate the FCSR in the architectural state
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if(addr == 3) {
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*data = this->get_fcsr();
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return iss::Ok;
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}
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return read_csr(addr, *reinterpret_cast<reg_t* const>(data));
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} break;
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case traits<BASE>::FENCE: {
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@ -822,6 +828,11 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
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case traits<BASE>::CSR: {
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if(length != sizeof(reg_t))
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return iss::Err;
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// We emulate the FCSR in the architectural state
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if(addr == 3) {
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this->set_fcsr(*data);
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return iss::Ok;
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}
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return write_csr(addr, *reinterpret_cast<const reg_t*>(data));
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} break;
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case traits<BASE>::FENCE: {
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