From 39d2518fdda2d8019cc1c25e1ce99cfafff079e3 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 28 Jul 2024 15:36:12 +0200
Subject: [PATCH] checkin: tgc5f builds and runs through

---
 gen_input/templates/interp/CORENAME.cpp.gtl |  7 ++++++-
 src/iss/arch/riscv_hart_m_p.h               | 11 +++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index 6804f57..8fcb64f 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -100,7 +100,12 @@ protected:
     using compile_ret_t = virt_addr_t;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
 
-    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+<%
+def fcsr = registers.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}     
+<%}%>
 
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 30c15e4..ed59015 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -39,6 +39,7 @@
 #include "iss/instrumentation_if.h"
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
+#include "iss/vm_types.h"
 #include "riscv_hart_common.h"
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
@@ -691,6 +692,11 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
                 return iss::Err;
+            // We emulate the FCSR in the architectural state
+            if(addr == 3) {
+                *data = this->get_fcsr();
+                return iss::Ok;
+            }
             return read_csr(addr, *reinterpret_cast<reg_t* const>(data));
         } break;
         case traits<BASE>::FENCE: {
@@ -822,6 +828,11 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
                 return iss::Err;
+            // We emulate the FCSR in the architectural state
+            if(addr == 3) {
+                this->set_fcsr(*data);
+                return iss::Ok;
+            }
             return write_csr(addr, *reinterpret_cast<const reg_t*>(data));
         } break;
         case traits<BASE>::FENCE: {