fixes build system to handle TCC properly
This commit is contained in:
parent
145a0cf68b
commit
b4b03f7850
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@ -32,49 +32,41 @@ add_subdirectory(softfloat)
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set(LIB_SOURCES
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src/iss/plugin/instruction_count.cpp
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src/iss/arch/tgc_c.cpp
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src/vm/tcc/vm_tgc_c.cpp
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src/vm/interp/vm_tgc_c.cpp
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src/vm/fp_functions.cpp
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)
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if(WITH_TCC)
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list(APPEND LIB_SOURCES src/vm/tcc/vm_tgc_c.cpp)
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endif()
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# library files
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if(TARGET ${CORE_NAME}_cpp)
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list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
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else()
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FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
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FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
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list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
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foreach(FILEPATH ${GEN_ISS_SOURCES})
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get_filename_component(CORE ${FILEPATH} NAME_WE)
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string(TOUPPER ${CORE} CORE)
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list(APPEND LIB_DEFINES CORE_${CORE})
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endforeach()
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message("Core defines are ${LIB_DEFINES}")
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FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
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FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
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list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
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foreach(FILEPATH ${GEN_ISS_SOURCES})
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get_filename_component(CORE ${FILEPATH} NAME_WE)
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string(TOUPPER ${CORE} CORE)
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list(APPEND LIB_DEFINES CORE_${CORE})
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endforeach()
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message("Core defines are ${LIB_DEFINES}")
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if(WITH_LLVM)
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FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
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list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
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endif()
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if(WITH_TCC)
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FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
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list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
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endif()
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if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
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list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
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endif()
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if(WITH_LLVM)
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FILE(GLOB LLVM_GEN_SOURCES
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${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
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)
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list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
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endif()
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if(WITH_TCC)
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FILE(GLOB TCC_GEN_SOURCES
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${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
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)
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list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
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endif()
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# Define the library
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add_library(${PROJECT_NAME} ${LIB_SOURCES})
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# list code gen dependencies
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if(TARGET ${CORE_NAME}_cpp)
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add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
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endif()
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if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
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target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
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@ -185,11 +177,17 @@ install(TARGETS tgc-sim
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#
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###############################################################################
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if(TARGET scc-sysc)
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project(dbt-rise-tgc_sc VERSION 1.0.0)
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if(BUILD_SHARED_LIBS)
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set(THIS_PROJECT_NAME dbt-rise-tgc_sc)
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else()
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set(THIS_PROJECT_NAME dbt-rise-tgc_sc_lib)
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endif()
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project(${THIS_PROJECT_NAME} VERSION 1.0.0)
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add_library(${PROJECT_NAME}
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src/sysc/core_complex.cpp
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src/sysc/register_tgc_c.cpp
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)
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target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src)
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target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
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target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
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foreach(F IN LISTS TGC_SOURCES)
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@ -219,5 +217,14 @@ if(TARGET scc-sysc)
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PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package)
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INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
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)
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if(NOT BUILD_SHARED_LIBS)
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add_library(dbt-rise-tgc_sc INTERFACE)
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target_include_directories(dbt-rise-tgc_sc INTERFACE $<TARGET_PROPERTY:${THIS_PROJECT_NAME},INTERFACE_INCLUDE_DIRECTORIES>)
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target_include_directories(dbt-rise-tgc_sc INTERFACE $<TARGET_PROPERTY:dbt-rise-tgc,INTERFACE_INCLUDE_DIRECTORIES>)
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target_link_libraries(dbt-rise-tgc_sc INTERFACE
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-Wl,--whole-archive,$<TARGET_FILE:${THIS_PROJECT_NAME}>,--no-whole-archive
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$<TARGET_PROPERTY:${THIS_PROJECT_NAME},INTERFACE_LINK_LIBRARIES>
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scc-sysc)
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endif()
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endif()
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@ -304,7 +304,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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return pc;
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}
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}
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} // namespace ${coreDef.name.toLowerCase()}
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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@ -301,7 +301,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
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tu("return *next_pc;");
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}
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} // namespace mnrv32
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} // namespace ${coreDef.name.toLowerCase()}
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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@ -37,10 +37,11 @@
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#include <iss/debugger/target_adapter_if.h>
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#include <iss/iss.h>
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#include <iss/vm_types.h>
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#include <iss/factory.h>
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#ifndef WIN32
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#include <iss/plugin/loader.h>
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#endif
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#include "core_complex.h"
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#include "sc_core_adapter_if.h"
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#include <iss/arch/tgc_mapper.h>
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#include <scc/report.h>
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#include <util/ities.h>
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@ -85,136 +86,9 @@ using namespace sc_core;
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namespace {
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iss::debugger::encoder_decoder encdec;
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std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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}
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template<typename PLAT>
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class core_wrapper_t : public PLAT {
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public:
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using reg_t = typename arch::traits<typename PLAT::core>::reg_t;
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using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
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using heart_state_t = typename PLAT::hart_state_type;
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core_wrapper_t(core_complex *owner)
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: owner(owner) { }
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uint32_t get_mode() { return this->reg.PRIV; }
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inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
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inline bool get_interrupt_execution() { return this->interrupt_sim; }
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heart_state_t &get_state() { return this->state; }
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void notify_phase(iss::arch_if::exec_phase p) override {
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if (p == iss::arch_if::ISTART)
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owner->sync(this->instr_if.get_total_cycles());
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}
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sync_type needed_sync() const override { return PRE_SYNC; }
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void disass_output(uint64_t pc, const std::string instr) override {
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if (!owner->disass_output(pc, instr)) {
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std::stringstream s;
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s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
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<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
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<< this->reg.icount + this->cycle_offset << "]";
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SCCDEBUG(owner->name())<<"disass: "
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<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
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<< std::setfill(' ') << std::left << instr << s.str();
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}
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};
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status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
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if (addr.access && access_type::DEBUG)
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return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
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else {
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return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? Ok : Err;
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}
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}
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status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
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if (addr.access && access_type::DEBUG)
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return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
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else {
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auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
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// clear MTIP on mtimecmp write
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if (addr.val == 0x2004000) {
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reg_t val;
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this->read_csr(arch::mip, val);
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if (val & (1ULL << 7)) this->write_csr(arch::mip, val & ~(1ULL << 7));
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}
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return res;
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}
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}
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status read_csr(unsigned addr, reg_t &val) override {
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#ifndef CWR_SYSTEMC
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if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
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uint64_t time_val;
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bool ret = owner->mtime_o->nb_peek(time_val);
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if (addr == iss::arch::time) {
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val = static_cast<reg_t>(time_val);
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} else if (addr == iss::arch::timeh) {
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if (sizeof(reg_t) != 4) return iss::Err;
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val = static_cast<reg_t>(time_val >> 32);
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}
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return ret?Ok:Err;
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#else
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if((addr==arch::time || addr==arch::timeh)){
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uint64_t time_val = owner->mtime_i.read();
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if (addr == iss::arch::time) {
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val = static_cast<reg_t>(time_val);
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} else if (addr == iss::arch::timeh) {
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if (sizeof(reg_t) != 4) return iss::Err;
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val = static_cast<reg_t>(time_val >> 32);
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}
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return Ok;
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#endif
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} else {
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return PLAT::read_csr(addr, val);
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}
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}
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void wait_until(uint64_t flags) override {
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SCCDEBUG(owner->name()) << "Sleeping until interrupt";
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while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
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sc_core::wait(wfi_evt);
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}
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PLAT::wait_until(flags);
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}
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void local_irq(short id, bool value) {
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reg_t mask = 0;
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switch (id) {
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case 3: // SW
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mask = 1 << 3;
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break;
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case 7: // timer
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mask = 1 << 7;
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break;
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case 11: // external
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mask = 1 << 11;
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break;
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default:
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if(id>15) mask = 1 << id;
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break;
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}
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if (value) {
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this->csr[arch::mip] |= mask;
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wfi_evt.notify();
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} else
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this->csr[arch::mip] &= ~mask;
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this->check_interrupt();
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if(value)
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SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
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}
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private:
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core_complex *const owner;
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sc_event wfi_evt;
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};
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int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func df,
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debugger::target_adapter_if *tgt_adapter) {
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if (argc > 1) {
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@ -262,45 +136,34 @@ public:
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std::function<void(bool)> set_interrupt_execution;
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std::function<void(short, bool)> local_irq;
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template<typename PLAT>
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std::tuple<cpu_ptr, vm_ptr> create_core(std::string const& backend, unsigned gdb_port, uint32_t hart_id){
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auto* lcpu = new core_wrapper_t<PLAT>(owner);
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lcpu->set_mhartid(hart_id);
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get_mode = [lcpu]() { return lcpu->get_mode(); };
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get_state = [lcpu]() { return lcpu->get_state().mstatus.backing.val; };
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get_interrupt_execution = [lcpu]() { return lcpu->get_interrupt_execution(); };
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set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
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local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
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if(backend == "interp")
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return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
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#ifdef WITH_LLVM
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if(backend == "llvm")
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return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
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#endif
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#ifdef WITH_TCC
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if(backend == "tcc")
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s return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
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#endif
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return {nullptr, nullptr};
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}
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void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
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CREATE_CORE(tgc_c)
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#ifdef CORE_TGC_B
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CREATE_CORE(tgc_b)
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#endif
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#ifdef CORE_TGC_D
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CREATE_CORE(tgc_d)
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#endif
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#ifdef CORE_TGC_D_XRB_MAC
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CREATE_CORE(tgc_d_xrb_mac)
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#endif
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#ifdef CORE_TGC_D_XRB_NN
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CREATE_CORE(tgc_d_xrb_nn)
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#endif
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{
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LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
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auto & f = iss::core_factory::instance();
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if(type.size()==0 || type == "?") {
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std::cout<<"Available cores: "<<util::join(f.get_names(), ", ")<<std::endl;
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sc_core::sc_stop();
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} else if (type.find('|') != std::string::npos) {
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std::tie(cpu, vm) = f.create(type+"|"+backend);
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} else {
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auto base_isa = type.substr(0, 5);
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if(base_isa=="tgc_d" || base_isa=="tgc_e") {
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std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port);
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} else {
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std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port);
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}
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}
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if(!cpu ){
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SCCFATAL() << "Could not create cpu for isa " << type << " and backend " <<backend;
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}
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if(!vm ){
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SCCFATAL() << "Could not create vm for isa " << type << " and backend " <<backend;
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}
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reinterpret_cast<sc_core_adapter_if&>(*cpu).set_mhartid(hart_id);
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get_mode = [this]() { return reinterpret_cast<sc_core_adapter_if&>(*cpu).get_mode(); };
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get_state = [this]() { return reinterpret_cast<sc_core_adapter_if&>(*cpu).get_state(); };
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get_interrupt_execution = [this]() { return reinterpret_cast<sc_core_adapter_if&>(*cpu).get_interrupt_execution(); };
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set_interrupt_execution = [this](bool b) { return reinterpret_cast<sc_core_adapter_if&>(*cpu).set_interrupt_execution(b); };
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local_irq = [this](short s, bool b) { return reinterpret_cast<sc_core_adapter_if&>(*cpu).local_irq(s, b); };
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auto *srv = debugger::server<debugger::gdb_session>::get();
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if (srv) tgt_adapter = srv->get_target();
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if (tgt_adapter)
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@ -634,5 +497,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
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gp.set_streaming_width(length);
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return dbus->transport_dbg(gp) == length;
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}
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} /* namespace SiFive */
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} /* namespace tgfs */
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} /* namespace sysc */
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@ -38,28 +38,34 @@
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#include "core_complex.h"
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namespace iss {
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namespace {
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volatile std::array<bool, 4> dummy = {
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namespace interp {
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volatile std::array<bool, 2> tgc_init = {
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core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{interp::create(cpu, gdb_port)}};
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return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
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}),
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core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{interp::create(cpu, gdb_port)}};
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}),
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return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
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})
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};
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}
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#if defined(WITH_TCC)
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namespace tcc {
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volatile std::array<bool, 2> tgc_init = {
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core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
|
||||
return {cpu_ptr{cpu}, vm_ptr{tcc::create(cpu, gdb_port)}};
|
||||
return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
|
||||
}),
|
||||
core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
|
||||
return {cpu_ptr{cpu}, vm_ptr{tcc::create(cpu, gdb_port)}};
|
||||
return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
|
||||
})
|
||||
};
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -11,14 +11,13 @@
|
|||
|
||||
#include <scc/report.h>
|
||||
#include <util/ities.h>
|
||||
#include "core_complex.h"
|
||||
#include "sc_core_adapter_if.h"
|
||||
#include <iss/iss.h>
|
||||
#include <iss/vm_types.h>
|
||||
#include <iostream>
|
||||
|
||||
|
||||
template<typename PLAT>
|
||||
class sc_core_adapter : public PLAT {
|
||||
class sc_core_adapter : public PLAT, public sc_core_adapter_if {
|
||||
public:
|
||||
using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
|
||||
using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
|
||||
|
@ -26,13 +25,15 @@ public:
|
|||
sc_core_adapter(sysc::tgfs::core_complex *owner)
|
||||
: owner(owner) { }
|
||||
|
||||
uint32_t get_mode() { return this->reg.PRIV; }
|
||||
void set_mhartid(unsigned id) override { PLAT::set_mhartid(id); }
|
||||
|
||||
inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
|
||||
uint32_t get_mode() override { return this->reg.PRIV; }
|
||||
|
||||
inline bool get_interrupt_execution() { return this->interrupt_sim; }
|
||||
void set_interrupt_execution(bool v) override { this->interrupt_sim = v?1:0; }
|
||||
|
||||
heart_state_t &get_state() { return this->state; }
|
||||
bool get_interrupt_execution() override { return this->interrupt_sim; }
|
||||
|
||||
uint64_t get_state() override { return this->state.mstatus.backing.val; }
|
||||
|
||||
void notify_phase(iss::arch_if::exec_phase p) override {
|
||||
if (p == iss::arch_if::ISTART)
|
||||
|
@ -113,7 +114,7 @@ public:
|
|||
PLAT::wait_until(flags);
|
||||
}
|
||||
|
||||
void local_irq(short id, bool value) {
|
||||
void local_irq(short id, bool value) override {
|
||||
reg_t mask = 0;
|
||||
switch (id) {
|
||||
case 3: // SW
|
||||
|
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* sc_core_adapter.h
|
||||
*
|
||||
* Created on: Jul 5, 2023
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef _SYSC_SC_CORE_ADAPTER_IF_H_
|
||||
#define _SYSC_SC_CORE_ADAPTER_IF_H_
|
||||
|
||||
|
||||
#include <scc/report.h>
|
||||
#include <util/ities.h>
|
||||
#include "core_complex.h"
|
||||
#include <iss/iss.h>
|
||||
#include <iss/vm_types.h>
|
||||
#include <iostream>
|
||||
|
||||
struct sc_core_adapter_if {
|
||||
virtual void set_mhartid(unsigned) = 0;
|
||||
virtual uint32_t get_mode() = 0;
|
||||
virtual uint64_t get_state() = 0;
|
||||
virtual bool get_interrupt_execution() = 0;
|
||||
virtual void set_interrupt_execution(bool v) = 0;
|
||||
virtual void local_irq(short id, bool value) = 0;
|
||||
virtual ~sc_core_adapter_if() = default;
|
||||
};
|
||||
|
||||
|
||||
#endif /* _SYSC_SC_CORE_ADAPTER_IF_H_ */
|
|
@ -3210,7 +3210,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
|
|||
tu("return *next_pc;");
|
||||
}
|
||||
|
||||
} // namespace mnrv32
|
||||
} // namespace tgc_c
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
|
||||
|
@ -3218,7 +3218,7 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
|
|||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
} // namesapce tcc
|
||||
} // namespace tcc
|
||||
} // namespace iss
|
||||
|
||||
#include <iss/factory.h>
|
||||
|
|
Loading…
Reference in New Issue