fix mip handling
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fd98ad95f6
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2d7973520b
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@ -781,13 +781,14 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
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val = csr[mie];
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_hartid(unsigned addr, reg_t &val) {
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val = mhartid_reg;
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_hartid(unsigned addr, reg_t &val) {
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val = mhartid_reg;
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
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auto mask = get_irq_mask();
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val = csr[mie] & mask;
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return iss::Ok;
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}
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@ -799,13 +800,14 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
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val = csr[mip];
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auto mask = get_irq_mask();
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val = csr[mip] & mask;
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
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auto mask = get_irq_mask();
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mask &= ~(1 << 7); // MTIP is read only
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mask &= 0xf; // only xSIP is writable
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csr[mip] = (csr[mip] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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@ -181,7 +181,7 @@ public:
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};
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using hart_state_type = hart_state<reg_t>;
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constexpr reg_t get_irq_wrmask(size_t mode) {
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constexpr reg_t get_irq_mask(size_t mode) {
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std::array<const reg_t, 4> m = {{
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0b000100010001, // U mode
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0b001100110011, // S mode
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@ -925,7 +925,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
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auto mask = get_irq_wrmask((addr >> 8) & 0x3);
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auto mask = get_irq_mask((addr >> 8) & 0x3);
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val = csr[mie] & mask;
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if(this->reg.PRIV!=3)
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val &= csr[mideleg];
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@ -933,14 +933,14 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
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auto mask = get_irq_wrmask((addr >> 8) & 0x3);
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auto mask = get_irq_mask((addr >> 8) & 0x3);
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csr[mie] = (csr[mie] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
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auto mask = get_irq_wrmask((addr >> 8) & 0x3);
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auto mask = get_irq_mask((addr >> 8) & 0x3);
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val = csr[mip] & mask;
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if(this->reg.PRIV!=3)
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val &= csr[mideleg];
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@ -948,10 +948,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
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auto mask = get_irq_wrmask((addr >> 8) & 0x3);
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mask &= ~(8 << 4); // MTIP is read only
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if(this->reg.PRIV!=3)
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mask &= ~(3 << 4); // STIP and UTIP are read only in user and supervisor mode
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auto mask = get_irq_mask((addr >> 8) & 0x3);
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mask &= 0xf; // only xSIP is writable
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csr[mip] = (csr[mip] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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