integrates new tval changes
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9996fd4833
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375755999a
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@ -117,7 +117,12 @@ protected:
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this->core.wait_until(type);
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}
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inline void set_tval(uint64_t new_tval){
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tval = new_tval;
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}
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uint64_t fetch_count{0};
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uint64_t tval{0};
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using yield_t = boost::coroutines2::coroutine<void>::push_type;
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using coro_t = boost::coroutines2::coroutine<void>::pull_type;
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@ -341,7 +346,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// this->core.reg.trap_state = this->core.reg.pending_trap;
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// trap check
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if(trap_state!=0){
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super::core.enter_trap(trap_state, pc.val, instr);
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//In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
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auto mcause = (trap_state>>16) & 0xff;
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super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
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} else {
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icount++;
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instret++;
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@ -1207,7 +1207,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
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}
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}
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template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
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template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
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// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
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// calculate and write mcause val
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auto const trap_id = bit_sub<0, 16>(flags);
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@ -1228,10 +1228,10 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
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*/
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switch(cause) {
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case 0:
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csr[mtval] = static_cast<reg_t>(addr);
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csr[mtval] = static_cast<reg_t>(tval);
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break;
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case 2:
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csr[mtval] = (!has_compressed() || (instr & 0x3) == 3) ? instr : instr & 0xffff;
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csr[mtval] = (!has_compressed() || (tval & 0x3) == 3) ? tval : tval & 0xffff;
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break;
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case 3:
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if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
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@ -113,7 +113,12 @@ protected:
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this->core.wait_until(type);
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}
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inline void set_tval(uint64_t new_tval){
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tval = new_tval;
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}
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uint64_t fetch_count{0};
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uint64_t tval{0};
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using yield_t = boost::coroutines2::coroutine<void>::push_type;
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using coro_t = boost::coroutines2::coroutine<void>::pull_type;
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@ -463,14 +468,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
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}
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else {
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if(imm % traits::INSTR_ALIGNMENT) {
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uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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if(rd != 0) {
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*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 ));
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}
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) ));
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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}
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}
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@ -500,6 +507,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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uint32_t addr_mask = (uint32_t)- 2;
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uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )) & (int64_t)(addr_mask ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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@ -534,11 +542,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(*(X+rs1) == *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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}
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}
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@ -567,11 +577,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(*(X+rs1) != *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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}
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}
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@ -600,11 +612,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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}
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}
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@ -633,11 +647,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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}
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}
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@ -666,11 +682,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(*(X+rs1) < *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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}
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}
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@ -699,11 +717,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(*(X+rs1) >= *(X+rs2)) {
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if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
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uint32_t new_pc = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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if(new_pc % traits::INSTR_ALIGNMENT) {
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set_tval(new_pc);
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raise(0, 0);
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}
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else {
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*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
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*NEXT_PC = new_pc;
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this->core.reg.last_branch = 1;
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}
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}
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@ -2675,7 +2695,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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// this->core.reg.trap_state = this->core.reg.pending_trap;
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// trap check
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if(trap_state!=0){
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super::core.enter_trap(trap_state, pc.val, instr);
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//In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
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auto mcause = (trap_state>>16) & 0xff;
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super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
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} else {
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icount++;
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instret++;
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