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DBT-RISE-TGC
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adapts to changes of instrumentation interface in dbt-rise-core

This commit is contained in:
Eyck Jentzsch 2023-04-22 17:04:41 +02:00
parent 54f75f92ea
commit 00b0f101ac
11 changed files with 83 additions and 43 deletions
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4
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -146,18 +146,17 @@ protected:
inline void process_spawn_blocks() {
if(spawn_blocks.size()==0) return;
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
if(*it){
(*it)();
++it;
} else
spawn_blocks.erase(it);
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
@ -263,6 +262,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto inst_id = decode_inst_id(instr);
// pre execution stuff
this->core.last_branch = 0;
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
case arch::traits<ARCH>::opcode_e::${instr.name}: {

6
src/iss/arch/riscv_hart_m_p.h
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2021 MINRES Technologies GmbH
* Copyright (C) 2019 - 2023 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -316,7 +316,9 @@ protected:
uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
bool is_branch_taken() override { return arch.last_branch; };
riscv_hart_m_p<BASE, FEAT> &arch;
};

6
src/iss/arch/riscv_hart_msu_vp.h
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
* Copyright (C) 2017 - 2023 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -340,7 +340,9 @@ protected:
uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
bool is_branch_taken() override { return arch.last_branch; };
riscv_hart_msu_vp<BASE> &arch;
};

6
src/iss/arch/riscv_hart_mu_p.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2021 MINRES Technologies GmbH
* Copyright (C) 2017 - 2023 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -340,7 +340,9 @@ protected:
uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
bool is_branch_taken() override { return arch.last_branch; };
riscv_hart_mu_p<BASE, FEAT> &arch;
};

12
src/iss/plugin/cycle_estimate.cpp
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -107,12 +107,12 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
}
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const& exc_info) {
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
assert(instr_if && "No instrumentation interface available but callback executed");
auto entry = delays[instr_info.instr_id];
bool taken = exc_info.branch_taken;
if (exc_info.branch_taken && (entry.taken > 1))
instr_if->set_curr_instr_cycles(entry.taken);
bool taken = instr_if->is_branch_taken();
if (taken && (entry.taken > 1))
instr_if->update_last_instr_cycles(entry.taken);
else if (entry.not_taken > 1)
instr_if->set_curr_instr_cycles(entry.not_taken);
instr_if->update_last_instr_cycles(entry.not_taken);
}

4
src/iss/plugin/cycle_estimate.h
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -78,7 +78,7 @@ public:
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t instr_info, exec_info const&) override;
void callback(instr_info_t instr_info) override;
private:
iss::instrumentation_if *instr_if;

4
src/iss/plugin/instruction_count.cpp
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH
* Copyright (C) 2017 - 2023 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
return true;
}
void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
rep_counts[instr_info.instr_id]++;
}

4
src/iss/plugin/instruction_count.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -69,7 +69,7 @@ public:
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t, exec_info const&) override;
void callback(instr_info_t) override;
private:
Json::Value root;

44
src/iss/plugin/pctrace.cpp
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@ -1,3 +1,37 @@
/*******************************************************************************
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contributors:
* alex.com - initial implementation
******************************************************************************/
#include <iss/arch_if.h>
#include <iss/plugin/pctrace.h>
#include <util/logging.h>
@ -152,22 +186,22 @@ bool pctrace::registration(const char *const version, vm_if& vm) {
return true;
}
void pctrace::callback(instr_info_t iinfo, const exec_info& einfo) {
void pctrace::callback(instr_info_t iinfo) {
auto delay = 0;
size_t id = iinfo.instr_id;
auto entry = delays[id];
auto instr = instr_if->get_instr_word();
auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
bool taken = einfo.branch_taken;
bool taken = instr_if->is_branch_taken();
bool compressed = (instr&0x3)!=0x3;
if (einfo.branch_taken) {
if (taken) {
delay = entry.taken;
if(entry.taken > 1)
instr_if->set_curr_instr_cycles(entry.taken);
instr_if->update_last_instr_cycles(entry.taken);
} else {
delay = entry.not_taken;
if (entry.not_taken > 1)
instr_if->set_curr_instr_cycles(entry.not_taken);
instr_if->update_last_instr_cycles(entry.not_taken);
}
#ifndef WITH_LZ4
output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";

4
src/iss/plugin/pctrace.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -83,7 +83,7 @@ public:
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t, exec_info const&) override;
void callback(instr_info_t) override;
private:
iss::instrumentation_if *instr_if {nullptr};

32
src/vm/interp/vm_tgc_c.cpp
View File

@ -140,16 +140,15 @@ protected:
inline void process_spawn_blocks() {
if(spawn_blocks.size()==0) return;
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
if(*it){
(*it)();
++it;
} else
spawn_blocks.erase(it);
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
}
private:
/****************************************************************************
* start opcode definitions
@ -341,6 +340,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto inst_id = decode_inst_id(instr);
// pre execution stuff
this->core.last_branch = 0;
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
switch(inst_id){
case arch::traits<ARCH>::opcode_e::LUI: {
@ -422,7 +422,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd) = *PC + 4;
}
*NEXT_PC = *PC + (int32_t)sext<21>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -457,7 +457,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd) = *PC + 4;
}
*NEXT_PC = new_pc & ~ 0x1;
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -489,7 +489,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -522,7 +522,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -555,7 +555,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -588,7 +588,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -621,7 +621,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -654,7 +654,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
}
@ -2097,7 +2097,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
*(X+1) = *PC + 2;
*NEXT_PC = *PC + (int16_t)sext<12>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
TRAP_CJAL:break;
}// @suppress("No break at end of case")
@ -2342,7 +2342,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
*NEXT_PC = *PC + (int16_t)sext<12>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
TRAP_CJ:break;
}// @suppress("No break at end of case")
@ -2363,7 +2363,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
if(*(X+rs1 + 8) == 0) {
*NEXT_PC = *PC + (int16_t)sext<9>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
TRAP_CBEQZ:break;
@ -2385,7 +2385,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
if(*(X+rs1 + 8) != 0) {
*NEXT_PC = *PC + (int16_t)sext<9>(imm);
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
TRAP_CBNEZ:break;
@ -2485,7 +2485,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
{
if(rs1 && rs1 < traits::RFS) {
*NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1;
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
else {
raise(0, 2);
@ -2553,7 +2553,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint32_t new_pc = *(X+rs1);
*(X+1) = *PC + 2;
*NEXT_PC = new_pc & ~ 0x1;
super::ex_info.branch_taken=true;
this->core.last_branch = 1;
}
}
TRAP_CJALR:break;