From 00b0f101ac92c3c125957ab94449efd4c742b94e Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 22 Apr 2023 17:04:41 +0200 Subject: [PATCH] adapts to changes of instrumentation interface in dbt-rise-core --- gen_input/templates/interp/CORENAME.cpp.gtl | 4 +- src/iss/arch/riscv_hart_m_p.h | 6 ++- src/iss/arch/riscv_hart_msu_vp.h | 6 ++- src/iss/arch/riscv_hart_mu_p.h | 6 ++- src/iss/plugin/cycle_estimate.cpp | 12 +++--- src/iss/plugin/cycle_estimate.h | 4 +- src/iss/plugin/instruction_count.cpp | 4 +- src/iss/plugin/instruction_count.h | 4 +- src/iss/plugin/pctrace.cpp | 44 ++++++++++++++++++--- src/iss/plugin/pctrace.h | 4 +- src/vm/interp/vm_tgc_c.cpp | 32 +++++++-------- 11 files changed, 83 insertions(+), 43 deletions(-) diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 7a3f88f..7b26430 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -146,18 +146,17 @@ protected: inline void process_spawn_blocks() { if(spawn_blocks.size()==0) return; - std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken); for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);) if(*it){ (*it)(); ++it; } else spawn_blocks.erase(it); - std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken); } <%functions.each{ it.eachLine { %> ${it}<%}%> <%}%> + private: /**************************************************************************** * start opcode definitions @@ -263,6 +262,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' auto inst_id = decode_inst_id(instr); // pre execution stuff + this->core.last_branch = 0; if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %> case arch::traits::opcode_e::${instr.name}: { diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 5967c29..74e20c0 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2021 MINRES Technologies GmbH + * Copyright (C) 2019 - 2023 MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -316,7 +316,9 @@ protected: uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; } - void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; + void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; + + bool is_branch_taken() override { return arch.last_branch; }; riscv_hart_m_p &arch; }; diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 54e93fd..f09ea99 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH + * Copyright (C) 2017 - 2023 MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -340,7 +340,9 @@ protected: uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; } - virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; }; + void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; + + bool is_branch_taken() override { return arch.last_branch; }; riscv_hart_msu_vp &arch; }; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index fc2f16e..040999d 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2021 MINRES Technologies GmbH + * Copyright (C) 2017 - 2023 MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -340,7 +340,9 @@ protected: uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; } - void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; + void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; + + bool is_branch_taken() override { return arch.last_branch; }; riscv_hart_mu_p &arch; }; diff --git a/src/iss/plugin/cycle_estimate.cpp b/src/iss/plugin/cycle_estimate.cpp index 3174f30..77d4c5b 100644 --- a/src/iss/plugin/cycle_estimate.cpp +++ b/src/iss/plugin/cycle_estimate.cpp @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2017, MINRES Technologies GmbH + * Copyright (C) 2017 - 2023, MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -107,12 +107,12 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& } -void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const& exc_info) { +void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) { assert(instr_if && "No instrumentation interface available but callback executed"); auto entry = delays[instr_info.instr_id]; - bool taken = exc_info.branch_taken; - if (exc_info.branch_taken && (entry.taken > 1)) - instr_if->set_curr_instr_cycles(entry.taken); + bool taken = instr_if->is_branch_taken(); + if (taken && (entry.taken > 1)) + instr_if->update_last_instr_cycles(entry.taken); else if (entry.not_taken > 1) - instr_if->set_curr_instr_cycles(entry.not_taken); + instr_if->update_last_instr_cycles(entry.not_taken); } diff --git a/src/iss/plugin/cycle_estimate.h b/src/iss/plugin/cycle_estimate.h index f35f106..079a805 100644 --- a/src/iss/plugin/cycle_estimate.h +++ b/src/iss/plugin/cycle_estimate.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2017, 2018, MINRES Technologies GmbH + * Copyright (C) 2017 - 2023, MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -78,7 +78,7 @@ public: sync_type get_sync() override { return POST_SYNC; }; - void callback(instr_info_t instr_info, exec_info const&) override; + void callback(instr_info_t instr_info) override; private: iss::instrumentation_if *instr_if; diff --git a/src/iss/plugin/instruction_count.cpp b/src/iss/plugin/instruction_count.cpp index 0b54e21..7613b27 100644 --- a/src/iss/plugin/instruction_count.cpp +++ b/src/iss/plugin/instruction_count.cpp @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2017, MINRES Technologies GmbH + * Copyright (C) 2017 - 2023 MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_ return true; } -void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) { +void iss::plugin::instruction_count::callback(instr_info_t instr_info) { rep_counts[instr_info.instr_id]++; } diff --git a/src/iss/plugin/instruction_count.h b/src/iss/plugin/instruction_count.h index 6e90cf6..94504cf 100644 --- a/src/iss/plugin/instruction_count.h +++ b/src/iss/plugin/instruction_count.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2017, 2018, MINRES Technologies GmbH + * Copyright (C) 2017 - 2023, MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -69,7 +69,7 @@ public: sync_type get_sync() override { return POST_SYNC; }; - void callback(instr_info_t, exec_info const&) override; + void callback(instr_info_t) override; private: Json::Value root; diff --git a/src/iss/plugin/pctrace.cpp b/src/iss/plugin/pctrace.cpp index df2225a..ea20702 100644 --- a/src/iss/plugin/pctrace.cpp +++ b/src/iss/plugin/pctrace.cpp @@ -1,3 +1,37 @@ +/******************************************************************************* + * Copyright (C) 2017 - 2023, MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Contributors: + * alex.com - initial implementation + ******************************************************************************/ + #include #include #include @@ -152,22 +186,22 @@ bool pctrace::registration(const char *const version, vm_if& vm) { return true; } -void pctrace::callback(instr_info_t iinfo, const exec_info& einfo) { +void pctrace::callback(instr_info_t iinfo) { auto delay = 0; size_t id = iinfo.instr_id; auto entry = delays[id]; auto instr = instr_if->get_instr_word(); auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6) - bool taken = einfo.branch_taken; + bool taken = instr_if->is_branch_taken(); bool compressed = (instr&0x3)!=0x3; - if (einfo.branch_taken) { + if (taken) { delay = entry.taken; if(entry.taken > 1) - instr_if->set_curr_instr_cycles(entry.taken); + instr_if->update_last_instr_cycles(entry.taken); } else { delay = entry.not_taken; if (entry.not_taken > 1) - instr_if->set_curr_instr_cycles(entry.not_taken); + instr_if->update_last_instr_cycles(entry.not_taken); } #ifndef WITH_LZ4 output<get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n"; diff --git a/src/iss/plugin/pctrace.h b/src/iss/plugin/pctrace.h index ff3153c..092719d 100644 --- a/src/iss/plugin/pctrace.h +++ b/src/iss/plugin/pctrace.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2017, 2018, MINRES Technologies GmbH + * Copyright (C) 2017 - 2023, MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -83,7 +83,7 @@ public: sync_type get_sync() override { return POST_SYNC; }; - void callback(instr_info_t, exec_info const&) override; + void callback(instr_info_t) override; private: iss::instrumentation_if *instr_if {nullptr}; diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp index eaef390..3e54a25 100644 --- a/src/vm/interp/vm_tgc_c.cpp +++ b/src/vm/interp/vm_tgc_c.cpp @@ -140,16 +140,15 @@ protected: inline void process_spawn_blocks() { if(spawn_blocks.size()==0) return; - std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken); for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);) if(*it){ (*it)(); ++it; } else spawn_blocks.erase(it); - std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken); } + private: /**************************************************************************** * start opcode definitions @@ -341,6 +340,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' auto inst_id = decode_inst_id(instr); // pre execution stuff + this->core.last_branch = 0; if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); switch(inst_id){ case arch::traits::opcode_e::LUI: { @@ -422,7 +422,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *(X+rd) = *PC + 4; } *NEXT_PC = *PC + (int32_t)sext<21>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -457,7 +457,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *(X+rd) = *PC + 4; } *NEXT_PC = new_pc & ~ 0x1; - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -489,7 +489,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { *NEXT_PC = *PC + (int16_t)sext<13>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -522,7 +522,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { *NEXT_PC = *PC + (int16_t)sext<13>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -555,7 +555,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { *NEXT_PC = *PC + (int16_t)sext<13>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -588,7 +588,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { *NEXT_PC = *PC + (int16_t)sext<13>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -621,7 +621,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { *NEXT_PC = *PC + (int16_t)sext<13>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -654,7 +654,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { *NEXT_PC = *PC + (int16_t)sext<13>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } } @@ -2097,7 +2097,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { *(X+1) = *PC + 2; *NEXT_PC = *PC + (int16_t)sext<12>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } TRAP_CJAL:break; }// @suppress("No break at end of case") @@ -2342,7 +2342,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { *NEXT_PC = *PC + (int16_t)sext<12>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } TRAP_CJ:break; }// @suppress("No break at end of case") @@ -2363,7 +2363,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { if(*(X+rs1 + 8) == 0) { *NEXT_PC = *PC + (int16_t)sext<9>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } TRAP_CBEQZ:break; @@ -2385,7 +2385,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { if(*(X+rs1 + 8) != 0) { *NEXT_PC = *PC + (int16_t)sext<9>(imm); - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } TRAP_CBNEZ:break; @@ -2485,7 +2485,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { if(rs1 && rs1 < traits::RFS) { *NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1; - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } else { raise(0, 2); @@ -2553,7 +2553,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co uint32_t new_pc = *(X+rs1); *(X+1) = *PC + 2; *NEXT_PC = new_pc & ~ 0x1; - super::ex_info.branch_taken=true; + this->core.last_branch = 1; } } TRAP_CJALR:break;