fixes according to fixed generator
This commit is contained in:
parent
d881cb6e63
commit
c5465bf9e2
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@ -363,7 +363,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = (int32_t)imm;
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*(X+rd) = (uint32_t)((int32_t)imm);
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}
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}
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}
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@ -448,7 +448,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t new_pc = (*(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm)) & ~ 0x1;
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uint32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1;
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if(new_pc % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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@ -483,7 +483,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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if(*(X+rs1 % traits::RFS) == *(X+rs2 % traits::RFS)) {
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if(*(X+rs1) == *(X+rs2)) {
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if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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@ -516,7 +516,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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if(*(X+rs1 % traits::RFS) != *(X+rs2 % traits::RFS)) {
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if(*(X+rs1) != *(X+rs2)) {
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if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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@ -549,7 +549,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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if((int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)) {
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if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
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if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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@ -582,7 +582,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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if((int32_t)*(X+rs1 % traits::RFS) >= (int32_t)*(X+rs2 % traits::RFS)) {
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if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
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if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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@ -615,7 +615,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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if(*(X+rs1 % traits::RFS) < *(X+rs2 % traits::RFS)) {
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if(*(X+rs1) < *(X+rs2)) {
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if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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@ -648,7 +648,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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if(*(X+rs1 % traits::RFS) >= *(X+rs2 % traits::RFS)) {
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if(*(X+rs1) >= *(X+rs2)) {
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if(imm % traits::INSTR_ALIGNMENT) {
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raise(0, 0);
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}
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@ -681,12 +681,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LB;
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int8_t res = (int8_t)read_res;
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if(rd != 0) {
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*(X+rd) = (int32_t)res;
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*(X+rd) = (uint32_t)res;
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}
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}
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}
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@ -712,12 +712,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LH;
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int16_t res = (int16_t)read_res;
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if(rd != 0) {
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*(X+rd) = (int32_t)res;
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*(X+rd) = (uint32_t)res;
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}
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}
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}
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@ -743,12 +743,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LW;
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int32_t res = (int32_t)read_res;
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if(rd != 0) {
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*(X+rd) = (int32_t)res;
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*(X+rd) = (uint32_t)res;
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}
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}
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}
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@ -774,7 +774,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LBU;
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uint8_t res = (uint8_t)read_res;
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@ -805,7 +805,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
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if(this->core.trap_state>=0x80000000UL) goto TRAP_LHU;
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uint16_t res = (uint16_t)read_res;
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@ -836,8 +836,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2 % traits::RFS));
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uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
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super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2));
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if(this->core.trap_state>=0x80000000UL) goto TRAP_SB;
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}
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}
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@ -863,8 +863,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2 % traits::RFS));
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uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
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super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2));
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if(this->core.trap_state>=0x80000000UL) goto TRAP_SH;
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}
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}
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@ -890,8 +890,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2 % traits::RFS));
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uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
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super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2));
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if(this->core.trap_state>=0x80000000UL) goto TRAP_SW;
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}
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}
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@ -918,7 +918,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm);
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*(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
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}
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}
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}
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@ -945,7 +945,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = ((int32_t)*(X+rs1 % traits::RFS) < (int16_t)sext<12>(imm))? 1 : 0;
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*(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0;
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}
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}
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}
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@ -972,7 +972,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = (*(X+rs1 % traits::RFS) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
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*(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
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}
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}
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}
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@ -999,7 +999,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) ^ (int16_t)sext<12>(imm);
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*(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm));
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}
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}
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}
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@ -1026,7 +1026,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) | (int16_t)sext<12>(imm);
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*(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm));
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}
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}
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}
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@ -1053,7 +1053,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) & (int16_t)sext<12>(imm);
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*(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm));
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}
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}
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}
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@ -1080,7 +1080,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) << shamt;
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*(X+rd) = *(X+rs1) << shamt;
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}
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}
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}
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@ -1107,7 +1107,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) >> shamt;
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*(X+rd) = *(X+rs1) >> shamt;
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}
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}
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}
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@ -1134,7 +1134,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = (int32_t)*(X+rs1 % traits::RFS) >> shamt;
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*(X+rd) = (int32_t)*(X+rs1) >> shamt;
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}
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}
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}
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@ -1161,7 +1161,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) + *(X+rs2 % traits::RFS);
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*(X+rd) = *(X+rs1) + *(X+rs2);
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}
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}
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}
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@ -1188,7 +1188,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) - *(X+rs2 % traits::RFS);
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*(X+rd) = *(X+rs1) - *(X+rs2);
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}
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}
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}
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@ -1215,7 +1215,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) << (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
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*(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
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}
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}
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}
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@ -1241,13 +1241,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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*(X+rd) = (int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)? 1 : 0;
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}
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if(rd != 0) {
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*(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
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}
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}
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}
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@ -1274,7 +1269,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = (uint32_t)*(X+rs1 % traits::RFS) < (uint32_t)*(X+rs2 % traits::RFS)? 1 : 0;
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*(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
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}
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}
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}
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@ -1301,7 +1296,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) ^ *(X+rs2 % traits::RFS);
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*(X+rd) = *(X+rs1) ^ *(X+rs2);
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}
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}
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}
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@ -1328,7 +1323,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
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*(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
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}
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}
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}
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@ -1355,7 +1350,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = (int32_t)*(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1));
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*(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
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}
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}
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}
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@ -1382,7 +1377,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) | *(X+rs2 % traits::RFS);
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*(X+rd) = *(X+rs1) | *(X+rs2);
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}
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}
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}
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@ -1409,7 +1404,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1 % traits::RFS) & *(X+rs2 % traits::RFS);
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*(X+rd) = *(X+rs1) & *(X+rs2);
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}
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}
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}
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@ -1509,7 +1504,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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raise(0, 2);
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}
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else {
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uint32_t xrs1 = *(X+rs1 % traits::RFS);
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uint32_t xrs1 = *(X+rs1);
|
||||
if(rd != 0) {
|
||||
uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW;
|
||||
|
|
@ -1549,7 +1544,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS;
|
||||
uint32_t xrd = read_res;
|
||||
uint32_t xrs1 = *(X+rs1 % traits::RFS);
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
if(rs1 != 0) {
|
||||
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
|
||||
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS;
|
||||
|
|
@ -1584,7 +1579,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
|
||||
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC;
|
||||
uint32_t xrd = read_res;
|
||||
uint32_t xrs1 = *(X+rs1 % traits::RFS);
|
||||
uint32_t xrs1 = *(X+rs1);
|
||||
if(rs1 != 0) {
|
||||
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
|
||||
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC;
|
||||
|
|
|
|||
Loading…
Reference in New Issue