fixed some issues in import script; added README for reference; added initial testbench script(to be improved)
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# requires conan version 1.59
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# requires decent cmake version 3.23 for instance
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git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
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cd TGC-ISS/
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setenv COWAREHOME /scratch/rocco/workarea/tools/synopsys/T-2022.06-3
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setenv SNPSLMD_LICENSE_FILE 27001@lic02.arteris.com:5285@lic-node0:5285@lic03:5285@lic-node1
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source $COWAREHOME/SLS/linux/setup.csh pae
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setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
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setenv PATH $COWAREHOME/common/bin/:${PATH}
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setenv LD_LIBRARY_PATH /scratch/rocco/workarea/tools/gcc-9.3.0-install/lib64/
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setenv CC /scratch/rocco/workarea/tools/synopsys/T-2022.06-3/SLS/linux/common/bin//gcc
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setenv CXX /scratch/rocco/workarea/tools/synopsys/T-2022.06-3/SLS/linux/common/bin//g++
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cmake -S . -B build/Debug-PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=/scratch/rocco/partners/minres/TGC-ISS/install
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cd build/Debug-PA/
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make -j 16 install
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cd ../../dbt-rise-tgc/contrib
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setenv TGFS_INSTALL_ROOT /scratch/rocco/partners/minres/TGC-ISS/install/
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# import the TGC core itself
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pct tgc_import.tcl
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@ -6,13 +6,10 @@ proc getScriptDirectory {} {
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set scriptFolder [file dirname $dispScriptFile]
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return $scriptFolder
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}
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if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
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set hardware /HARDWARE/HW/HW
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} else {
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set hardware /HARDWARE
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}
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set scriptDir [getScriptDirectory]
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#set top_design_name sysc::tgfs::core_complex
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set top_design_name core_complex
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set clocks clk_i
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set resets rst_i
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@ -38,13 +35,13 @@ foreach clock ${clocks} {
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foreach reset ${resets} {
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::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
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}
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::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
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#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
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# Set compile settings and look
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set block SYSTEM_LIBRARY:${top_design_name}
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::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
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::pct::set_encap_build_script $block/sysc::tgfs::${top_design_name} $scriptDir/build.tcl
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::pct::set_background_color_rgb $block 255 255 255 255
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::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name}
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::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} sysc::tgfs::${top_design_name} sysc::tgfs::${top_design_name}()
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# export the result as component
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::pct::export_system_library ${top_design_name} ${top_design_name}.xml
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source tgc_import.tcl
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::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
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::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
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::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
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{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::create_connection C i_core_complex/initiator i_Bus/i_core_complex_initiator
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::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
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::pct::create_connection C_1 i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
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#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
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#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
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::pct::create_simulation_build_config Debug
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::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
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# add build settings and save design for next steps
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#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs ${currentDir}/model/i_${Ncore_top_name}/Vgen_wrapper__ALL.a $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
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#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
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#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
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#::simulation::run_simulation Simulation
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#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
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#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
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#::pct::export_system "export"
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#::cd "export"
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#::scsh::open-project
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#::scsh::build
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#::scsh::elab sim
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::pct::save_system testbench.xml
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