DBT-RISE/DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

fixed some issues in import script; added README for reference; added initial testbench script(to be improved)

Browse Source
This commit is contained in:
Rocco Jonack 2023-04-19 05:20:58 -07:00
parent 8ff55d7b92
commit 0304aac9e5
3 changed files with 52 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
contrib/README.md Normal file
View File

@ -0,0 +1,19 @@
# requires conan version 1.59
# requires decent cmake version 3.23 for instance
git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
cd TGC-ISS/
setenv COWAREHOME /scratch/rocco/workarea/tools/synopsys/T-2022.06-3
setenv SNPSLMD_LICENSE_FILE 27001@lic02.arteris.com:5285@lic-node0:5285@lic03:5285@lic-node1
source $COWAREHOME/SLS/linux/setup.csh pae
setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
setenv PATH $COWAREHOME/common/bin/:${PATH}
setenv LD_LIBRARY_PATH /scratch/rocco/workarea/tools/gcc-9.3.0-install/lib64/
setenv CC /scratch/rocco/workarea/tools/synopsys/T-2022.06-3/SLS/linux/common/bin//gcc
setenv CXX /scratch/rocco/workarea/tools/synopsys/T-2022.06-3/SLS/linux/common/bin//g++
cmake -S . -B build/Debug-PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=/scratch/rocco/partners/minres/TGC-ISS/install
cd build/Debug-PA/
make -j 16 install
cd ../../dbt-rise-tgc/contrib
setenv TGFS_INSTALL_ROOT /scratch/rocco/partners/minres/TGC-ISS/install/
# import the TGC core itself
pct tgc_import.tcl

11
contrib/tgc_import.tcl
View File

@ -6,13 +6,10 @@ proc getScriptDirectory {} {
set scriptFolder [file dirname $dispScriptFile]
return $scriptFolder
}
if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
set hardware /HARDWARE/HW/HW
} else {
set hardware /HARDWARE
}
set scriptDir [getScriptDirectory]
#set top_design_name sysc::tgfs::core_complex
set top_design_name core_complex
set clocks clk_i
set resets rst_i
@ -38,13 +35,13 @@ foreach clock ${clocks} {
foreach reset ${resets} {
::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
}
::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
# Set compile settings and look
set block SYSTEM_LIBRARY:${top_design_name}
::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
::pct::set_encap_build_script $block/sysc::tgfs::${top_design_name} $scriptDir/build.tcl
::pct::set_background_color_rgb $block 255 255 255 255
::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name}
::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} sysc::tgfs::${top_design_name} sysc::tgfs::${top_design_name}()
# export the result as component
::pct::export_system_library ${top_design_name} ${top_design_name}.xml

29
contrib/tgc_import_tb.pct Normal file
View File

@ -0,0 +1,29 @@
source tgc_import.tcl
::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
::pct::create_connection C i_core_complex/initiator i_Bus/i_core_complex_initiator
::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
::pct::create_connection C_1 i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
::pct::create_simulation_build_config Debug
::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
# add build settings and save design for next steps
#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs ${currentDir}/model/i_${Ncore_top_name}/Vgen_wrapper__ALL.a $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
#::simulation::run_simulation Simulation
#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
#::pct::export_system "export"
#::cd "export"
#::scsh::open-project
#::scsh::build
#::scsh::elab sim
::pct::save_system testbench.xml