30 lines
1.9 KiB
Plaintext
30 lines
1.9 KiB
Plaintext
source tgc_import.tcl
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::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
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::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
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::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
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{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::create_connection C i_core_complex/initiator i_Bus/i_core_complex_initiator
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::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
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::pct::create_connection C_1 i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
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#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
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#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
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::pct::create_simulation_build_config Debug
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::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
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# add build settings and save design for next steps
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#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs ${currentDir}/model/i_${Ncore_top_name}/Vgen_wrapper__ALL.a $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
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#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
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#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
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#::simulation::run_simulation Simulation
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#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
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#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
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#::pct::export_system "export"
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#::cd "export"
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#::scsh::open-project
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#::scsh::build
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#::scsh::elab sim
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::pct::save_system testbench.xml
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