source tgc_import.tcl ::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic ::paultra::add_hw_instance Bus:Bus -inst_name i_Bus ::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \ { common_configuration:BackBone:/advanced/num_resources_per_target:1 } ::pct::create_connection C i_core_complex/initiator i_Bus/i_core_complex_initiator ::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10 ::pct::create_connection C_1 i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM #::pct::set_main_configuration Default {{#include } {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}} #::pct::set_main_configuration Debug {{#include } {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}} ::pct::create_simulation_build_config Debug ::pct::set_simulation_build_project_setting Debug "Main Configuration" Default # add build settings and save design for next steps #::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs ${currentDir}/model/i_${Ncore_top_name}/Vgen_wrapper__ALL.a $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp" #::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/ #::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"] #::simulation::run_simulation Simulation #::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST} #::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false #::pct::export_system "export" #::cd "export" #::scsh::open-project #::scsh::build #::scsh::elab sim ::pct::save_system testbench.xml