DBT-RISE/DBT-RISE-TGC
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moves pending interrupt check before handling trap thus saving 1 cycle

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This commit is contained in:
Eyck Jentzsch 2022-10-15 10:47:35 +02:00
parent 1a0fc4bd5d
commit 7113683ee0
2 changed files with 4 additions and 2 deletions
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3
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -289,6 +289,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// post execution stuff
process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
if(!this->core.trap_state) // update trap state if there is a pending interrupt
this->core.trap_state = this->core.pending_trap;
// trap check
if(trap_state!=0){
super::core.enter_trap(trap_state, pc.val, instr);
@ -299,7 +301,6 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
cycle++;
pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.trap_state = this->core.pending_trap;
}
}
return pc;

3
src/vm/interp/vm_tgc_c.cpp
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@ -2318,6 +2318,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// post execution stuff
process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
if(!this->core.trap_state) // update trap state if there is a pending interrupt
this->core.trap_state = this->core.pending_trap;
// trap check
if(trap_state!=0){
super::core.enter_trap(trap_state, pc.val, instr);
@ -2328,7 +2330,6 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
cycle++;
pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.trap_state = this->core.pending_trap;
}
}
return pc;