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DBT-RISE-TGC
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update core definitions to include Zicsr and Zifencei (#276)

This commit is contained in:
Eyck Jentzsch 2021-10-30 12:56:31 +02:00
parent 334d3fb296
commit a20f39e847
5 changed files with 5 additions and 5 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

@ -1 +1 @@
Subproject commit 9e3119a8064e8515eeca7e5298f88d0d9d224458
Subproject commit e7aaec6ad9336bd83b4da63dd0c96f8d11887661

2
gen_input/TGC_B.core_desc
View File

@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_B provides RV32I {
Core TGC_B provides RV32I, Zicsr, Zifencei {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper

2
gen_input/TGC_C.core_desc
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_C provides RV32I, RV32M, RV32IC {
Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper

2
gen_input/TGC_D.core_desc
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_D provides RV32I, RV32M, RV32IC {
Core TGC_D provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper

2
gen_input/TGC_D_XRB_MAC.core_desc
View File

@ -62,7 +62,7 @@ InstructionSet X_RB_MAC extends RISCVBase {
}
}
Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper